1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Motorola MC5282EVB board. 4 * 5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef _CONFIG_M5282EVB_H 13#define _CONFIG_M5282EVB_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19#define CONFIG_MCFTMR 20 21#define CONFIG_MCFUART 22#define CONFIG_SYS_UART_PORT (0) 23 24#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 25 26/* Configuration for environment 27 * Environment is embedded in u-boot in the second sector of the flash 28 */ 29#define CONFIG_ENV_ADDR 0xffe04000 30#define CONFIG_ENV_SIZE 0x2000 31 32#define LDS_BOARD_TEXT \ 33 . = DEFINED(env_offset) ? env_offset : .; \ 34 env/embedded.o(.text*); 35 36/* 37 * BOOTP options 38 */ 39#define CONFIG_BOOTP_BOOTFILESIZE 40 41/* 42 * Command line configuration. 43 */ 44 45#define CONFIG_MCFFEC 46#ifdef CONFIG_MCFFEC 47# define CONFIG_MII_INIT 1 48# define CONFIG_SYS_DISCOVER_PHY 49# define CONFIG_SYS_RX_ETH_BUFFER 8 50# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 51 52# define CONFIG_SYS_FEC0_PINMUX 0 53# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 54# define MCFFEC_TOUT_LOOP 50000 55/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 56# ifndef CONFIG_SYS_DISCOVER_PHY 57# define FECDUPLEX FULL 58# define FECSPEED _100BASET 59# else 60# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 61# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 62# endif 63# endif /* CONFIG_SYS_DISCOVER_PHY */ 64#endif 65 66#ifdef CONFIG_MCFFEC 67# define CONFIG_IPADDR 192.162.1.2 68# define CONFIG_NETMASK 255.255.255.0 69# define CONFIG_SERVERIP 192.162.1.1 70# define CONFIG_GATEWAYIP 192.162.1.1 71#endif /* CONFIG_MCFFEC */ 72 73#define CONFIG_HOSTNAME "M5282EVB" 74#define CONFIG_EXTRA_ENV_SETTINGS \ 75 "netdev=eth0\0" \ 76 "loadaddr=10000\0" \ 77 "u-boot=u-boot.bin\0" \ 78 "load=tftp ${loadaddr) ${u-boot}\0" \ 79 "upd=run load; run prog\0" \ 80 "prog=prot off ffe00000 ffe3ffff;" \ 81 "era ffe00000 ffe3ffff;" \ 82 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 83 "save\0" \ 84 "" 85 86#define CONFIG_SYS_LOAD_ADDR 0x20000 87 88#define CONFIG_SYS_MEMTEST_START 0x400 89#define CONFIG_SYS_MEMTEST_END 0x380000 90 91#define CONFIG_SYS_CLK 64000000 92 93/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ 94 95#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 96#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 97 98/* 99 * Low Level Configuration Settings 100 * (address mappings, register initial values, etc.) 101 * You should know what you are doing if you make changes here. 102 */ 103#define CONFIG_SYS_MBAR 0x40000000 104 105/*----------------------------------------------------------------------- 106 * Definitions for initial stack pointer and data area (in DPRAM) 107 */ 108#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 109#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 110#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 111#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 112 113/*----------------------------------------------------------------------- 114 * Start addresses for the final memory configuration 115 * (Set up by the startup code) 116 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 117 */ 118#define CONFIG_SYS_SDRAM_BASE 0x00000000 119#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 120#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 121#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 122#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 123 124/* If M5282 port is fully implemented the monitor base will be behind 125 * the vector table. */ 126#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) 127#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 128#else 129#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ 130#endif 131 132#define CONFIG_SYS_MONITOR_LEN 0x20000 133#define CONFIG_SYS_MALLOC_LEN (256 << 10) 134#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 135 136/* 137 * For booting Linux, the board info and command line data 138 * have to be in the first 8 MB of memory, since this is 139 * the maximum mapped by the Linux kernel during initialization ?? 140 */ 141#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 142 143/*----------------------------------------------------------------------- 144 * FLASH organization 145 */ 146#ifdef CONFIG_SYS_FLASH_CFI 147 148# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 149# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 150# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 151# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 152# define CONFIG_SYS_FLASH_CHECKSUM 153# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 154#endif 155 156/*----------------------------------------------------------------------- 157 * Cache Configuration 158 */ 159#define CONFIG_SYS_CACHELINE_SIZE 16 160 161#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 162 CONFIG_SYS_INIT_RAM_SIZE - 8) 163#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 164 CONFIG_SYS_INIT_RAM_SIZE - 4) 165#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 166#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 167 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 168 CF_ACR_EN | CF_ACR_SM_ALL) 169#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 170 CF_CACR_CEIB | CF_CACR_DBWE | \ 171 CF_CACR_EUSP) 172 173/*----------------------------------------------------------------------- 174 * Memory bank definitions 175 */ 176#define CONFIG_SYS_CS0_BASE 0xFFE00000 177#define CONFIG_SYS_CS0_CTRL 0x00001980 178#define CONFIG_SYS_CS0_MASK 0x001F0001 179 180/*----------------------------------------------------------------------- 181 * Port configuration 182 */ 183#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 184#define CONFIG_SYS_PADDR 0x0000000 185#define CONFIG_SYS_PADAT 0x0000000 186 187#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 188#define CONFIG_SYS_PBDDR 0x0000000 189#define CONFIG_SYS_PBDAT 0x0000000 190 191#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 192#define CONFIG_SYS_PCDDR 0x0000000 193#define CONFIG_SYS_PCDAT 0x0000000 194 195#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 196#define CONFIG_SYS_PCDDR 0x0000000 197#define CONFIG_SYS_PCDAT 0x0000000 198 199#define CONFIG_SYS_PEHLPAR 0xC0 200#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ 201#define CONFIG_SYS_DDRUA 0x05 202#define CONFIG_SYS_PJPAR 0xFF 203 204#endif /* _CONFIG_M5282EVB_H */ 205