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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#include "../board/freescale/common/ics307_clk.h"
12
13#ifdef CONFIG_SDCARD
14#define CONFIG_SPL_FLUSH_IMAGE
15#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
16#define CONFIG_SPL_TEXT_BASE 0xf8f81000
17#define CONFIG_SPL_PAD_TO 0x20000
18#define CONFIG_SPL_MAX_SIZE (128 * 1024)
19#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
20#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
21#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
22#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
23#define CONFIG_SYS_MPC85XX_NO_RESETVEC
24#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
25#define CONFIG_SPL_MMC_BOOT
26#ifdef CONFIG_SPL_BUILD
27#define CONFIG_SPL_COMMON_INIT_DDR
28#endif
29#endif
30
31#ifdef CONFIG_SPIFLASH
32#define CONFIG_SPL_SPI_FLASH_MINIMAL
33#define CONFIG_SPL_FLUSH_IMAGE
34#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
35#define CONFIG_SPL_TEXT_BASE 0xf8f81000
36#define CONFIG_SPL_PAD_TO 0x20000
37#define CONFIG_SPL_MAX_SIZE (128 * 1024)
38#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
39#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
40#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
41#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
42#define CONFIG_SYS_MPC85XX_NO_RESETVEC
43#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
44#define CONFIG_SPL_SPI_BOOT
45#ifdef CONFIG_SPL_BUILD
46#define CONFIG_SPL_COMMON_INIT_DDR
47#endif
48#endif
49
50#define CONFIG_NAND_FSL_ELBC
51#define CONFIG_SYS_NAND_MAX_ECCPOS 56
52#define CONFIG_SYS_NAND_MAX_OOBFREE 5
53
54#ifdef CONFIG_NAND
55#ifdef CONFIG_TPL_BUILD
56#define CONFIG_SPL_NAND_BOOT
57#define CONFIG_SPL_FLUSH_IMAGE
58#define CONFIG_SPL_NAND_INIT
59#define CONFIG_SPL_COMMON_INIT_DDR
60#define CONFIG_SPL_MAX_SIZE (128 << 10)
61#define CONFIG_SPL_TEXT_BASE 0xf8f81000
62#define CONFIG_SYS_MPC85XX_NO_RESETVEC
63#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
64#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
65#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
66#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
67#elif defined(CONFIG_SPL_BUILD)
68#define CONFIG_SPL_INIT_MINIMAL
69#define CONFIG_SPL_FLUSH_IMAGE
70#define CONFIG_SPL_TEXT_BASE 0xff800000
71#define CONFIG_SPL_MAX_SIZE 4096
72#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
73#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
74#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
75#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
76#endif
77#define CONFIG_SPL_PAD_TO 0x20000
78#define CONFIG_TPL_PAD_TO 0x20000
79#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
80#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
81#endif
82
83
84
85#ifndef CONFIG_RESET_VECTOR_ADDRESS
86#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
87#endif
88
89#define CONFIG_PCIE1
90#define CONFIG_PCIE2
91#define CONFIG_PCIE3
92#define CONFIG_FSL_PCI_INIT
93#define CONFIG_FSL_PCIE_RESET
94#define CONFIG_SYS_PCI_64BIT
95
96#define CONFIG_ENABLE_36BIT_PHYS
97
98#ifdef CONFIG_PHYS_64BIT
99#define CONFIG_ADDR_MAP
100#define CONFIG_SYS_NUM_ADDR_MAP 16
101#endif
102
103#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
104#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
105#define CONFIG_ICS307_REFCLK_HZ 33333000
106
107
108
109
110#define CONFIG_L2_CACHE
111#define CONFIG_BTB
112
113#define CONFIG_SYS_MEMTEST_START 0x00000000
114#define CONFIG_SYS_MEMTEST_END 0x7fffffff
115
116#define CONFIG_SYS_CCSRBAR 0xffe00000
117#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
118
119
120
121#ifdef CONFIG_SPL_BUILD
122#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
123#endif
124
125
126#define CONFIG_DDR_SPD
127#define CONFIG_VERY_BIG_RAM
128
129#ifdef CONFIG_DDR_ECC
130#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
131#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
132#endif
133
134#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
135#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
136
137#define CONFIG_DIMM_SLOTS_PER_CTLR 1
138#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
139
140
141#define CONFIG_SYS_SPD_BUS_NUM 1
142#define SPD_EEPROM_ADDRESS 0x51
143
144
145#define CONFIG_SYS_SDRAM_SIZE 2048
146#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
147#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
148#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
149#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
150#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
151#define CONFIG_SYS_DDR_TIMING_3 0x00010000
152#define CONFIG_SYS_DDR_TIMING_0 0x40110104
153#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
154#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
155#define CONFIG_SYS_DDR_MODE_1 0x00441221
156#define CONFIG_SYS_DDR_MODE_2 0x00000000
157#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
158#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
159#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
160#define CONFIG_SYS_DDR_CONTROL 0xc7000008
161#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
162#define CONFIG_SYS_DDR_TIMING_4 0x00220001
163#define CONFIG_SYS_DDR_TIMING_5 0x02401400
164#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
165#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
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187
188
189#define CONFIG_SYS_FLASH_BASE 0xe8000000
190#ifdef CONFIG_PHYS_64BIT
191#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
192#else
193#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
194#endif
195
196#define CONFIG_FLASH_BR_PRELIM \
197 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
198#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
199
200#ifdef CONFIG_NAND
201#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM
202#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
203#else
204#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
205#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
206#endif
207
208#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
209#define CONFIG_SYS_FLASH_QUIET_TEST
210#define CONFIG_FLASH_SHOW_PROGRESS 45
211
212#define CONFIG_SYS_MAX_FLASH_BANKS 1
213#define CONFIG_SYS_MAX_FLASH_SECT 1024
214
215#ifndef CONFIG_SYS_MONITOR_BASE
216#ifdef CONFIG_SPL_BUILD
217#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
218#else
219#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
220#endif
221#endif
222
223#define CONFIG_SYS_FLASH_EMPTY_INFO
224
225
226#if defined(CONFIG_NAND_FSL_ELBC)
227#define CONFIG_SYS_NAND_BASE 0xff800000
228#ifdef CONFIG_PHYS_64BIT
229#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
230#else
231#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
232#endif
233
234#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
235#define CONFIG_SYS_MAX_NAND_DEVICE 1
236#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
237#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
238
239
240#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
241 | (2<<BR_DECC_SHIFT) \
242 | BR_PS_8 \
243 | BR_MS_FCM \
244 | BR_V)
245#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
246 | OR_FCM_PGS \
247 | OR_FCM_CSCT \
248 | OR_FCM_CST \
249 | OR_FCM_CHT \
250 | OR_FCM_SCY_1 \
251 | OR_FCM_TRLX \
252 | OR_FCM_EHTR)
253#ifdef CONFIG_NAND
254#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
255#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
256#else
257#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
258#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
259#endif
260
261#endif
262
263#define CONFIG_HWCONFIG
264
265#define CONFIG_FSL_NGPIXIS
266#define PIXIS_BASE 0xffdf0000
267#ifdef CONFIG_PHYS_64BIT
268#define PIXIS_BASE_PHYS 0xfffdf0000ull
269#else
270#define PIXIS_BASE_PHYS PIXIS_BASE
271#endif
272
273#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
274#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
275
276#define PIXIS_LBMAP_SWITCH 7
277#define PIXIS_LBMAP_MASK 0xF0
278#define PIXIS_LBMAP_ALTBANK 0x20
279#define PIXIS_SPD 0x07
280#define PIXIS_SPD_SYSCLK_MASK 0x07
281#define PIXIS_ELBC_SPI_MASK 0xc0
282#define PIXIS_SPI 0x80
283
284#define CONFIG_SYS_INIT_RAM_LOCK
285#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
286#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
287
288#define CONFIG_SYS_GBL_DATA_OFFSET \
289 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
290#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
291
292#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
293#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
294
295
296
297
298#if defined(CONFIG_SPL_BUILD)
299#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
300#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
301#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
302#define CONFIG_SYS_L2_SIZE (256 << 10)
303#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
304#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
305#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
306#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
307#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
308#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
309#elif defined(CONFIG_NAND)
310#ifdef CONFIG_TPL_BUILD
311#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
312#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
313#define CONFIG_SYS_L2_SIZE (256 << 10)
314#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
315#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
316#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
317#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
318#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
319#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
320#else
321#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
322#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
323#define CONFIG_SYS_L2_SIZE (256 << 10)
324#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
325#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
326#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
327#endif
328#endif
329#endif
330
331
332
333
334#define CONFIG_SYS_NS16550_SERIAL
335#define CONFIG_SYS_NS16550_REG_SIZE 1
336#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
337#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
338#define CONFIG_NS16550_MIN_FUNCTIONS
339#endif
340
341#define CONFIG_SYS_BAUDRATE_TABLE \
342 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
343
344#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
345#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
346
347
348
349#ifdef CONFIG_FSL_DIU_FB
350#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
351#define CONFIG_VIDEO_LOGO
352#define CONFIG_VIDEO_BMP_LOGO
353#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
354
355
356
357
358#undef CONFIG_SYS_FLASH_EMPTY_INFO
359#endif
360
361#ifdef CONFIG_ATI
362#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
363#define CONFIG_BIOSEMU
364#define CONFIG_ATI_RADEON_FB
365#define CONFIG_VIDEO_LOGO
366#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
367#endif
368
369
370#define CONFIG_SYS_I2C
371#define CONFIG_SYS_I2C_FSL
372#define CONFIG_SYS_FSL_I2C_SPEED 400000
373#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
374#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
375#define CONFIG_SYS_FSL_I2C2_SPEED 400000
376#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
377#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
378#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
379
380
381
382
383#define CONFIG_ID_EEPROM
384#define CONFIG_SYS_I2C_EEPROM_NXID
385#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
386#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
387#define CONFIG_SYS_EEPROM_BUS_NUM 1
388
389#define CONFIG_SF_DEFAULT_SPEED 10000000
390#define CONFIG_SF_DEFAULT_MODE 0
391
392
393
394
395
396
397
398#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
399#ifdef CONFIG_PHYS_64BIT
400#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
401#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
402#else
403#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
404#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
405#endif
406#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
407#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
408#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
409#ifdef CONFIG_PHYS_64BIT
410#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
411#else
412#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
413#endif
414#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
415
416
417#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
418#ifdef CONFIG_PHYS_64BIT
419#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
420#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
421#else
422#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
423#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
424#endif
425#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
426#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
427#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
428#ifdef CONFIG_PHYS_64BIT
429#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
430#else
431#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
432#endif
433#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
434
435
436#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
437#ifdef CONFIG_PHYS_64BIT
438#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
439#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
440#else
441#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
442#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
443#endif
444#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
445#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
446#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
447#ifdef CONFIG_PHYS_64BIT
448#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
449#else
450#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
451#endif
452#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
453
454#ifdef CONFIG_PCI
455#define CONFIG_PCI_INDIRECT_BRIDGE
456#define CONFIG_PCI_SCAN_SHOW
457#endif
458
459
460#define CONFIG_FSL_SATA_V2
461
462#define CONFIG_SYS_SATA_MAX_DEVICE 2
463#define CONFIG_SATA1
464#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
465#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
466#define CONFIG_SATA2
467#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
468#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
469
470#ifdef CONFIG_FSL_SATA
471#define CONFIG_LBA48
472#endif
473
474#ifdef CONFIG_MMC
475#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
476#endif
477
478#ifdef CONFIG_TSEC_ENET
479
480#define CONFIG_TSECV2
481
482#define CONFIG_TSEC1 1
483#define CONFIG_TSEC1_NAME "eTSEC1"
484#define CONFIG_TSEC2 1
485#define CONFIG_TSEC2_NAME "eTSEC2"
486
487#define TSEC1_PHY_ADDR 1
488#define TSEC2_PHY_ADDR 2
489
490#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
491#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
492
493#define TSEC1_PHYIDX 0
494#define TSEC2_PHYIDX 0
495
496#define CONFIG_ETHPRIME "eTSEC1"
497#endif
498
499
500
501
502
503
504
505
506#ifdef CONFIG_SPIFLASH
507#define CONFIG_ENV_SPI_BUS 0
508#define CONFIG_ENV_SPI_CS 0
509#define CONFIG_ENV_SPI_MAX_HZ 10000000
510#define CONFIG_ENV_SPI_MODE 0
511#define CONFIG_ENV_SIZE 0x2000
512#define CONFIG_ENV_OFFSET 0x100000
513#define CONFIG_ENV_SECT_SIZE 0x10000
514#elif defined(CONFIG_SDCARD)
515#define CONFIG_FSL_FIXED_MMC_LOCATION
516#define CONFIG_ENV_SIZE 0x2000
517#define CONFIG_SYS_MMC_ENV_DEV 0
518#elif defined(CONFIG_NAND)
519#ifdef CONFIG_TPL_BUILD
520#define CONFIG_ENV_SIZE 0x2000
521#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
522#else
523#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
524#endif
525#define CONFIG_ENV_OFFSET (1024 * 1024)
526#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
527#elif defined(CONFIG_SYS_RAMBOOT)
528#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
529#define CONFIG_ENV_SIZE 0x2000
530#else
531#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
532#define CONFIG_ENV_SIZE 0x2000
533#define CONFIG_ENV_SECT_SIZE 0x20000
534#endif
535
536#define CONFIG_LOADS_ECHO
537#define CONFIG_SYS_LOADS_BAUD_CHANGE
538
539
540
541
542#define CONFIG_HAS_FSL_DR_USB
543#ifdef CONFIG_HAS_FSL_DR_USB
544#ifdef CONFIG_USB_EHCI_HCD
545#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
546#define CONFIG_USB_EHCI_FSL
547#endif
548#endif
549
550
551
552
553#define CONFIG_SYS_LOAD_ADDR 0x2000000
554
555
556
557
558
559
560#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
561#define CONFIG_SYS_BOOTM_LEN (64 << 20)
562
563#ifdef CONFIG_CMD_KGDB
564#define CONFIG_KGDB_BAUDRATE 230400
565#endif
566
567
568
569
570
571#define CONFIG_HOSTNAME "p1022ds"
572#define CONFIG_ROOTPATH "/opt/nfsroot"
573#define CONFIG_BOOTFILE "uImage"
574#define CONFIG_UBOOTPATH u-boot.bin
575
576#define CONFIG_LOADADDR 1000000
577
578#define CONFIG_EXTRA_ENV_SETTINGS \
579 "netdev=eth0\0" \
580 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
581 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
582 "tftpflash=tftpboot $loadaddr $uboot && " \
583 "protect off $ubootaddr +$filesize && " \
584 "erase $ubootaddr +$filesize && " \
585 "cp.b $loadaddr $ubootaddr $filesize && " \
586 "protect on $ubootaddr +$filesize && " \
587 "cmp.b $loadaddr $ubootaddr $filesize\0" \
588 "consoledev=ttyS0\0" \
589 "ramdiskaddr=2000000\0" \
590 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
591 "fdtaddr=1e00000\0" \
592 "fdtfile=p1022ds.dtb\0" \
593 "bdev=sda3\0" \
594 "hwconfig=esdhc;audclk:12\0"
595
596#define CONFIG_HDBOOT \
597 "setenv bootargs root=/dev/$bdev rw " \
598 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
599 "tftp $loadaddr $bootfile;" \
600 "tftp $fdtaddr $fdtfile;" \
601 "bootm $loadaddr - $fdtaddr"
602
603#define CONFIG_NFSBOOTCOMMAND \
604 "setenv bootargs root=/dev/nfs rw " \
605 "nfsroot=$serverip:$rootpath " \
606 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
607 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
608 "tftp $loadaddr $bootfile;" \
609 "tftp $fdtaddr $fdtfile;" \
610 "bootm $loadaddr - $fdtaddr"
611
612#define CONFIG_RAMBOOTCOMMAND \
613 "setenv bootargs root=/dev/ram rw " \
614 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
615 "tftp $ramdiskaddr $ramdiskfile;" \
616 "tftp $loadaddr $bootfile;" \
617 "tftp $fdtaddr $fdtfile;" \
618 "bootm $loadaddr $ramdiskaddr $fdtaddr"
619
620#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
621
622#endif
623