1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2011 Andes Technology Corporation 4 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 6 */ 7 8#ifndef __CONFIG_H 9#define __CONFIG_H 10 11#include <asm/arch-ae3xx/ae3xx.h> 12 13/* 14 * CPU and Board Configuration Options 15 */ 16#define CONFIG_USE_INTERRUPT 17 18#define CONFIG_SKIP_LOWLEVEL_INIT 19 20#define CONFIG_SKIP_TRUNOFF_WATCHDOG 21 22#define CONFIG_ARCH_MAP_SYSMEM 23 24#define CONFIG_BOOTP_SEND_HOSTNAME 25#define CONFIG_BOOTP_SERVERIP 26 27#ifdef CONFIG_SKIP_LOWLEVEL_INIT 28#ifdef CONFIG_OF_CONTROL 29#undef CONFIG_OF_SEPARATE 30#define CONFIG_OF_EMBED 31#endif 32#endif 33 34/* 35 * Timer 36 */ 37#define CONFIG_SYS_CLK_FREQ 39062500 38#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 39 40/* 41 * Use Externel CLOCK or PCLK 42 */ 43#undef CONFIG_FTRTC010_EXTCLK 44 45#ifndef CONFIG_FTRTC010_EXTCLK 46#define CONFIG_FTRTC010_PCLK 47#endif 48 49#ifdef CONFIG_FTRTC010_EXTCLK 50#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 51#else 52#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 53#endif 54 55#define TIMER_LOAD_VAL 0xffffffff 56 57/* 58 * Real Time Clock 59 */ 60#define CONFIG_RTC_FTRTC010 61 62/* 63 * Real Time Clock Divider 64 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 65 */ 66#define OSC_5MHZ (5*1000000) 67#define OSC_CLK (4*OSC_5MHZ) 68#define RTC_DIV_COUNT (0.5) /* Why?? */ 69 70/* 71 * Serial console configuration 72 */ 73 74/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 75#define CONFIG_SYS_NS16550_SERIAL 76#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 77#ifndef CONFIG_DM_SERIAL 78#define CONFIG_SYS_NS16550_REG_SIZE -4 79#endif 80#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 81 82/* 83 * Miscellaneous configurable options 84 */ 85 86/* 87 * Size of malloc() pool 88 */ 89/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 90#define CONFIG_SYS_MALLOC_LEN (512 << 10) 91 92/* 93 * Physical Memory Map 94 */ 95#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 96 97#define PHYS_SDRAM_1 \ 98 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 99 100#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 101#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 102 103#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 104 105#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 106 GENERATED_GBL_DATA_SIZE) 107 108/* 109 * Load address and memory test area should agree with 110 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 111 */ 112#define CONFIG_SYS_LOAD_ADDR 0x300000 113 114/* memtest works on 63 MB in DRAM */ 115#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 116#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 117 118/* 119 * Static memory controller configuration 120 */ 121#define CONFIG_FTSMC020 122 123#ifdef CONFIG_FTSMC020 124#include <faraday/ftsmc020.h> 125 126#define CONFIG_SYS_FTSMC020_CONFIGS { \ 127 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 128 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 129} 130 131#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 132#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 133 FTSMC020_BANK_SIZE_32M | \ 134 FTSMC020_BANK_MBW_32) 135 136#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 137 FTSMC020_TPR_AST(1) | \ 138 FTSMC020_TPR_CTW(1) | \ 139 FTSMC020_TPR_ATI(1) | \ 140 FTSMC020_TPR_AT2(1) | \ 141 FTSMC020_TPR_WTC(1) | \ 142 FTSMC020_TPR_AHT(1) | \ 143 FTSMC020_TPR_TRNA(1)) 144#endif 145 146/* 147 * FLASH on ADP_AG101P is connected to BANK0 148 * Just disalbe the other BANK to avoid detection error. 149 */ 150#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 151 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 152 FTSMC020_BANK_SIZE_32M | \ 153 FTSMC020_BANK_MBW_32) 154 155#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 156 FTSMC020_TPR_CTW(3) | \ 157 FTSMC020_TPR_ATI(0xf) | \ 158 FTSMC020_TPR_AT2(3) | \ 159 FTSMC020_TPR_WTC(3) | \ 160 FTSMC020_TPR_AHT(3) | \ 161 FTSMC020_TPR_TRNA(0xf)) 162 163#define FTSMC020_BANK1_CONFIG (0x00) 164#define FTSMC020_BANK1_TIMING (0x00) 165#endif /* CONFIG_FTSMC020 */ 166 167/* 168 * FLASH and environment organization 169 */ 170/* use CFI framework */ 171 172#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 173#define CONFIG_SYS_CFI_FLASH_STATUS_POLL 174 175/* support JEDEC */ 176#ifdef CONFIG_CFI_FLASH 177#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 178#endif 179 180/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 181#define PHYS_FLASH_1 0x88000000 /* BANK 0 */ 182#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 183#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 184#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 185 186#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 187#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 188 189/* max number of memory banks */ 190/* 191 * There are 4 banks supported for this Controller, 192 * but we have only 1 bank connected to flash on board 193 */ 194#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 195#define CONFIG_SYS_MAX_FLASH_BANKS 1 196#endif 197#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 198 199/* max number of sectors on one chip */ 200#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 201#define CONFIG_SYS_MAX_FLASH_SECT 512 202 203/* environments */ 204#define CONFIG_ENV_SPI_BUS 0 205#define CONFIG_ENV_SPI_CS 0 206#define CONFIG_ENV_SPI_MAX_HZ 50000000 207#define CONFIG_ENV_SPI_MODE 0 208#define CONFIG_ENV_SECT_SIZE 0x1000 209#define CONFIG_ENV_OFFSET 0x140000 210#define CONFIG_ENV_SIZE 8192 211#define CONFIG_ENV_OVERWRITE 212 213 214/* SPI FLASH */ 215#define CONFIG_SF_DEFAULT_BUS 0 216#define CONFIG_SF_DEFAULT_CS 0 217#define CONFIG_SF_DEFAULT_SPEED 1000000 218#define CONFIG_SF_DEFAULT_MODE 0 219 220/* 221 * For booting Linux, the board info and command line data 222 * have to be in the first 16 MB of memory, since this is 223 * the maximum mapped by the Linux kernel during initialization. 224 */ 225 226/* Initial Memory map for Linux*/ 227#define CONFIG_SYS_BOOTMAPSZ (64 << 20) 228/* Increase max gunzip size */ 229#define CONFIG_SYS_BOOTM_LEN (64 << 20) 230 231#endif /* __CONFIG_H */ 232