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6
7#ifndef _CONFIG_KMP204X_H
8#define _CONFIG_KMP204X_H
9
10#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
11
12
13
14#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
15
16#define CONFIG_NAND_ECC_BCH
17
18
19#include "keymile-common.h"
20
21#define CONFIG_SYS_RAMBOOT
22#define CONFIG_RAMBOOT_PBL
23#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
24#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
25#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
26#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
27
28
29#define CONFIG_SYS_BOOK3E_HV
30#define CONFIG_FSL_CORENET
31
32#define CONFIG_SYS_FSL_CPC
33#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
34#define CONFIG_PCIE1
35#define CONFIG_PCIE3
36#define CONFIG_FSL_PCI_INIT
37#define CONFIG_SYS_PCI_64BIT
38
39#define CONFIG_SYS_DPAA_RMAN
40
41
42#define CONFIG_ENV_SPI_BUS 0
43#define CONFIG_ENV_SPI_CS 0
44#define CONFIG_ENV_SPI_MAX_HZ 20000000
45#define CONFIG_ENV_SPI_MODE 0
46#define CONFIG_ENV_OFFSET 0x100000
47#define CONFIG_ENV_SIZE 0x004000
48#define CONFIG_ENV_SECT_SIZE 0x010000
49#define CONFIG_ENV_OFFSET_REDUND 0x110000
50#define CONFIG_ENV_TOTAL_SIZE 0x020000
51
52#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
53
54#ifndef __ASSEMBLY__
55unsigned long get_board_sys_clk(unsigned long dummy);
56#endif
57#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
58
59
60
61
62#define CONFIG_SYS_CACHE_STASHING
63#define CONFIG_BACKSIDE_L2_CACHE
64#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
65#define CONFIG_BTB
66
67#define CONFIG_ENABLE_36BIT_PHYS
68
69#define CONFIG_ADDR_MAP
70#define CONFIG_SYS_NUM_ADDR_MAP 64
71
72#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
73
74
75
76
77#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
78#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
79 CONFIG_RAMBOOT_TEXT_BASE)
80#define CONFIG_SYS_L3_SIZE (1024 << 10)
81#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
82
83#define CONFIG_SYS_DCSRBAR 0xf0000000
84#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
85
86
87
88
89#define CONFIG_VERY_BIG_RAM
90#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
91#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
92
93#define CONFIG_DIMM_SLOTS_PER_CTLR 1
94#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
95
96#define CONFIG_DDR_SPD
97#define CONFIG_FSL_DDR_INTERACTIVE
98
99#define CONFIG_SYS_SPD_BUS_NUM 0
100#define SPD_EEPROM_ADDRESS 0x54
101#define CONFIG_SYS_SDRAM_SIZE 4096
102
103#define CONFIG_SYS_LOAD_ADDR 0x100000
104#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
105
106
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110
111
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117
118
119
120#define CONFIG_KM_ROOTFSSIZE 0x0
121
122#define CONFIG_KM_PNVRAM 0x80000
123
124#define CONFIG_KM_PHRAM 0x100000
125
126
127#define CONFIG_KM_RESERVED_PRAM 0x1000
128
129
130#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
131
132#define CONFIG_KM_CRAMFS_ADDR 0x2000000
133#define CONFIG_KM_KERNEL_ADDR 0x1000000
134#define CONFIG_KM_FDT_ADDR 0x1F80000
135
136
137
138
139
140
141#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
142
143
144#define CONFIG_NAND_FSL_ELBC
145#define CONFIG_SYS_NAND_BASE 0xffa00000
146#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
147
148#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
149#define CONFIG_SYS_MAX_NAND_DEVICE 1
150#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
151
152
153#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
154 | BR_PS_8 \
155 | BR_MS_FCM \
156 | BR_V)
157
158#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
159 | OR_FCM_BCTLD \
160 | OR_FCM_SCY_1 \
161 | OR_FCM_RST \
162 | OR_FCM_PGS \
163 | OR_FCM_CST)
164
165#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
166#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
167
168
169#define CONFIG_SYS_QRIO_BASE 0xfb000000
170#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
171
172#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
173 | BR_PS_8 \
174 | BR_DECC_OFF \
175 | BR_MS_GPCM \
176 | BR_V)
177
178#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB \
179 | OR_GPCM_BCTLD \
180 | OR_GPCM_ACS_DIV4 \
181 | OR_GPCM_SCY_2 \
182 | OR_GPCM_TRLX \
183 | OR_GPCM_EAD)
184
185#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM
186#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM
187
188#define CONFIG_MISC_INIT_F
189
190#define CONFIG_HWCONFIG
191
192
193#define CONFIG_L1_INIT_RAM
194#define CONFIG_SYS_INIT_RAM_LOCK
195#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
196#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
197#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
198
199#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
200 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
201 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
202#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
203
204#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
205 GENERATED_GBL_DATA_SIZE)
206#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
207
208#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
209#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
210#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
211
212
213
214
215
216#define CONFIG_SYS_NS16550_SERIAL
217#define CONFIG_SYS_NS16550_REG_SIZE 1
218#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
219
220#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
221#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
222#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
223#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
224
225#define CONFIG_KM_CONSOLE_TTY "ttyS0"
226
227
228
229#define CONFIG_SYS_I2C
230#define CONFIG_SYS_I2C_INIT_BOARD
231#define CONFIG_SYS_I2C_SPEED 100000
232#define CONFIG_SYS_NUM_I2C_BUSES 3
233#define CONFIG_SYS_I2C_MAX_HOPS 1
234#define CONFIG_SYS_I2C_FSL
235#define CONFIG_I2C_MULTI_BUS
236#define CONFIG_I2C_CMD_TREE
237#define CONFIG_SYS_FSL_I2C_SPEED 400000
238#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
239#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
240#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
241 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
242 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
243 }
244#ifndef __ASSEMBLY__
245void set_sda(int state);
246void set_scl(int state);
247int get_sda(void);
248int get_scl(void);
249#endif
250
251#define CONFIG_KM_IVM_BUS 1
252
253
254
255
256#define CONFIG_SPI_FLASH_BAR
257#define CONFIG_SF_DEFAULT_SPEED 20000000
258#define CONFIG_SF_DEFAULT_MODE 0
259
260
261
262
263
264
265
266#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
267#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
268#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
269#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
270#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
271#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
272#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
273#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
274
275
276#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
277#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
278#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
279#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
280#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
281#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
282#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
283#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
284
285
286#define CONFIG_SYS_BMAN_NUM_PORTALS 10
287#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
288#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
289#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
290#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
291#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
292#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
293#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
294#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
295 CONFIG_SYS_BMAN_CENA_SIZE)
296#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
297#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
298#define CONFIG_SYS_QMAN_NUM_PORTALS 10
299#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
300#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
301#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
302#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
303#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
304#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
305#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
306#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
307 CONFIG_SYS_QMAN_CENA_SIZE)
308#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
309#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
310
311#define CONFIG_SYS_DPAA_FMAN
312#define CONFIG_SYS_DPAA_PME
313
314
315
316
317#define CONFIG_SYS_QE_FW_IN_SPIFLASH
318#define CONFIG_SYS_FMAN_FW_ADDR 0x120000
319#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
320#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
321
322#define CONFIG_FMAN_ENET
323#define CONFIG_PHYLIB_10G
324
325#define CONFIG_PCI_INDIRECT_BRIDGE
326
327#define CONFIG_PCI_SCAN_SHOW
328
329
330#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
331#define CONFIG_SYS_TBIPA_VALUE 8
332#define CONFIG_ETHPRIME "FM1@DTSEC5"
333
334
335
336
337#define CONFIG_LOADS_ECHO
338#define CONFIG_SYS_LOADS_BAUD_CHANGE
339
340
341
342
343#define CONFIG_WATCHDOG
344#define CONFIG_WATCHDOG_PRESC 34
345#define CONFIG_WATCHDOG_RC WRC_CHIP
346
347
348
349
350
351
352
353#undef CONFIG_JFFS2_CMDLINE
354
355
356
357
358
359
360#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
361#define CONFIG_SYS_BOOTM_LEN (64 << 20)
362
363#ifdef CONFIG_CMD_KGDB
364#define CONFIG_KGDB_BAUDRATE 230400
365#endif
366
367#define __USB_PHY_TYPE utmi
368#define CONFIG_USB_EHCI_FSL
369
370
371
372
373#define CONFIG_ENV_OVERWRITE
374#ifndef CONFIG_KM_DEF_ENV
375#define CONFIG_KM_DEF_ENV "km-common=empty\0"
376#endif
377
378
379#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
380
381
382#define CONFIG_KM_DEF_ENV_CPU \
383 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
384 "cramfsloadfdt=" \
385 "cramfsload ${fdt_addr_r} " \
386 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
387 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
388 "u-boot="CONFIG_HOSTNAME "/u-boot.pbl\0" \
389 "update=" \
390 "sf probe 0;sf erase 0 +${filesize};" \
391 "sf write ${load_addr_r} 0 ${filesize};\0" \
392 "set_fdthigh=true\0" \
393 "checkfdt=true\0" \
394 ""
395
396#define CONFIG_HW_ENV_SETTINGS \
397 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
398 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
399 "usb_dr_mode=host\0"
400
401#define CONFIG_KM_NEW_ENV \
402 "newenv=sf probe 0;" \
403 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
404 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
405
406
407#ifndef CONFIG_KM_DEF_ARCH
408#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
409#endif
410
411#define CONFIG_EXTRA_ENV_SETTINGS \
412 CONFIG_KM_DEF_ENV \
413 CONFIG_KM_DEF_ARCH \
414 CONFIG_KM_NEW_ENV \
415 CONFIG_HW_ENV_SETTINGS \
416 "EEprom_ivm=pca9547:70:9\0" \
417 ""
418
419#endif
420