1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2016 Freescale Semiconductor 4 */ 5 6#ifndef __LS1046ARDB_H__ 7#define __LS1046ARDB_H__ 8 9#include "ls1046a_common.h" 10 11#define CONFIG_SYS_CLK_FREQ 100000000 12#define CONFIG_DDR_CLK_FREQ 100000000 13 14#define CONFIG_LAYERSCAPE_NS_ACCESS 15 16#define CONFIG_DIMM_SLOTS_PER_CTLR 1 17/* Physical Memory Map */ 18#define CONFIG_CHIP_SELECTS_PER_CTRL 4 19 20#define CONFIG_DDR_SPD 21#define SPD_EEPROM_ADDRESS 0x51 22#define CONFIG_SYS_SPD_BUS_NUM 0 23 24#define CONFIG_DDR_ECC 25#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 26#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 27#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 28#ifndef CONFIG_SPL 29#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 30#endif 31 32#ifdef CONFIG_SD_BOOT 33#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg 34#ifdef CONFIG_EMMC_BOOT 35#define CONFIG_SYS_FSL_PBL_RCW \ 36 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg 37#else 38#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg 39#endif 40#elif defined(CONFIG_QSPI_BOOT) 41#define CONFIG_SYS_FSL_PBL_RCW \ 42 board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg 43#define CONFIG_SYS_FSL_PBL_PBI \ 44 board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg 45#define CONFIG_SYS_UBOOT_BASE 0x40100000 46#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 47#endif 48 49#ifndef SPL_NO_IFC 50/* IFC */ 51#define CONFIG_FSL_IFC 52/* 53 * NAND Flash Definitions 54 */ 55#define CONFIG_NAND_FSL_IFC 56#endif 57 58#define CONFIG_SYS_NAND_BASE 0x7e800000 59#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 60 61#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 62#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 63 | CSPR_PORT_SIZE_8 \ 64 | CSPR_MSEL_NAND \ 65 | CSPR_V) 66#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 67#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 68 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 69 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 70 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 71 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 72 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 73 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 74 75#define CONFIG_SYS_NAND_ONFI_DETECTION 76 77#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 78 FTIM0_NAND_TWP(0x18) | \ 79 FTIM0_NAND_TWCHT(0x7) | \ 80 FTIM0_NAND_TWH(0xa)) 81#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 82 FTIM1_NAND_TWBE(0x39) | \ 83 FTIM1_NAND_TRR(0xe) | \ 84 FTIM1_NAND_TRP(0x18)) 85#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 86 FTIM2_NAND_TREH(0xa) | \ 87 FTIM2_NAND_TWHRE(0x1e)) 88#define CONFIG_SYS_NAND_FTIM3 0x0 89 90#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 91#define CONFIG_SYS_MAX_NAND_DEVICE 1 92#define CONFIG_MTD_NAND_VERIFY_WRITE 93 94#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 95 96/* 97 * CPLD 98 */ 99#define CONFIG_SYS_CPLD_BASE 0x7fb00000 100#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 101 102#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 103#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 104 CSPR_PORT_SIZE_8 | \ 105 CSPR_MSEL_GPCM | \ 106 CSPR_V) 107#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 108#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) 109 110/* CPLD Timing parameters for IFC GPCM */ 111#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 112 FTIM0_GPCM_TEADC(0x0e) | \ 113 FTIM0_GPCM_TEAHC(0x0e)) 114#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 115 FTIM1_GPCM_TRAD(0x3f)) 116#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 117 FTIM2_GPCM_TCH(0xf) | \ 118 FTIM2_GPCM_TWP(0x3E)) 119#define CONFIG_SYS_CPLD_FTIM3 0x0 120 121/* IFC Timing Params */ 122#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 123#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 124#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 125#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 126#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 127#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 128#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 129#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 130 131#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 132#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 133#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 134#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 135#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 136#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 137#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 138#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 139 140/* EEPROM */ 141#define CONFIG_ID_EEPROM 142#define CONFIG_SYS_I2C_EEPROM_NXID 143#define CONFIG_SYS_EEPROM_BUS_NUM 0 144#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 145#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 146#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 147#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 148#define I2C_RETIMER_ADDR 0x18 149 150/* PMIC */ 151#define CONFIG_POWER 152#ifdef CONFIG_POWER 153#define CONFIG_POWER_I2C 154#endif 155 156/* 157 * Environment 158 */ 159#ifndef SPL_NO_ENV 160#define CONFIG_ENV_OVERWRITE 161#endif 162 163#ifdef CONFIG_TFABOOT 164#define CONFIG_SYS_MMC_ENV_DEV 0 165 166#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 167#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ 168#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ 169#else 170#if defined(CONFIG_SD_BOOT) 171#define CONFIG_SYS_MMC_ENV_DEV 0 172#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 173#define CONFIG_ENV_SIZE 0x2000 174#else 175#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 176#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 177#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ 178#endif 179#endif 180 181#define AQR105_IRQ_MASK 0x80000000 182/* FMan */ 183#ifndef SPL_NO_FMAN 184 185#ifdef CONFIG_NET 186#define CONFIG_PHY_REALTEK 187#endif 188 189#ifdef CONFIG_SYS_DPAA_FMAN 190#define CONFIG_FMAN_ENET 191#define RGMII_PHY1_ADDR 0x1 192#define RGMII_PHY2_ADDR 0x2 193 194#define SGMII_PHY1_ADDR 0x3 195#define SGMII_PHY2_ADDR 0x4 196 197#define FM1_10GEC1_PHY_ADDR 0x0 198 199#define FDT_SEQ_MACADDR_FROM_ENV 200 201#define CONFIG_ETHPRIME "FM1@DTSEC3" 202#endif 203 204#endif 205 206/* QSPI device */ 207#ifndef SPL_NO_QSPI 208#ifdef CONFIG_FSL_QSPI 209#define CONFIG_SPI_FLASH_SPANSION 210#define FSL_QSPI_FLASH_SIZE (1 << 26) 211#define FSL_QSPI_FLASH_NUM 2 212#endif 213#endif 214 215#ifndef SPL_NO_MISC 216#undef CONFIG_BOOTCOMMAND 217#ifdef CONFIG_TFABOOT 218#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 219 "env exists secureboot && esbc_halt;;" 220#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ 221 "env exists secureboot && esbc_halt;" 222#else 223#if defined(CONFIG_QSPI_BOOT) 224#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 225 "env exists secureboot && esbc_halt;;" 226#elif defined(CONFIG_SD_BOOT) 227#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ 228 "env exists secureboot && esbc_halt;" 229#endif 230#endif 231#endif 232 233#include <asm/fsl_secure_boot.h> 234 235#endif /* __LS1046ARDB_H__ */ 236