LXR uboot/include/fsl

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
   4 *
   5 * Dave Liu <daveliu@freescale.com>
   6 * based on source code of Shlomi Gridish
   7 */
   8
   9#ifndef __QE_H__
  10#define __QE_H__
  11
  12#include "common.h"
  13#ifdef CONFIG_U_QE
  14#include <linux/immap_qe.h>
  15#endif
  16
  17#define QE_NUM_OF_BRGS  16
  18#define UCC_MAX_NUM     8
  19
  20#define QE_DATAONLY_BASE        0
  21#define QE_DATAONLY_SIZE        (QE_MURAM_SIZE - QE_DATAONLY_BASE)
  22
  23/* QE threads SNUM
  24*/
  25typedef enum qe_snum_state {
  26        QE_SNUM_STATE_USED,   /* used */
  27        QE_SNUM_STATE_FREE    /* free */
  28} qe_snum_state_e;
  29
  30typedef struct qe_snum {
  31        u8              num;   /* snum  */
  32        qe_snum_state_e state; /* state */
  33} qe_snum_t;
  34
  35/* QE RISC allocation
  36*/
  37#define QE_RISC_ALLOCATION_RISC1        0x1  /* RISC 1 */
  38#define QE_RISC_ALLOCATION_RISC2        0x2  /* RISC 2 */
  39#define QE_RISC_ALLOCATION_RISC3        0x4  /* RISC 3 */
  40#define QE_RISC_ALLOCATION_RISC4        0x8  /* RISC 4 */
  41#define QE_RISC_ALLOCATION_RISC1_AND_RISC2      (QE_RISC_ALLOCATION_RISC1 | \
  42                                                 QE_RISC_ALLOCATION_RISC2)
  43#define QE_RISC_ALLOCATION_FOUR_RISCS   (QE_RISC_ALLOCATION_RISC1 | \
  44                                         QE_RISC_ALLOCATION_RISC2 | \
  45                                         QE_RISC_ALLOCATION_RISC3 | \
  46                                         QE_RISC_ALLOCATION_RISC4)
  47
  48/* QE CECR commands for UCC fast.
  49*/
  50#define QE_CR_FLG                       0x00010000
  51#define QE_RESET                        0x80000000
  52#define QE_INIT_TX_RX                   0x00000000
  53#define QE_INIT_RX                      0x00000001
  54#define QE_INIT_TX                      0x00000002
  55#define QE_ENTER_HUNT_MODE              0x00000003
  56#define QE_STOP_TX                      0x00000004
  57#define QE_GRACEFUL_STOP_TX             0x00000005
  58#define QE_RESTART_TX                   0x00000006
  59#define QE_SWITCH_COMMAND               0x00000007
  60#define QE_SET_GROUP_ADDRESS            0x00000008
  61#define QE_INSERT_CELL                  0x00000009
  62#define QE_ATM_TRANSMIT                 0x0000000a
  63#define QE_CELL_POOL_GET                0x0000000b
  64#define QE_CELL_POOL_PUT                0x0000000c
  65#define QE_IMA_HOST_CMD                 0x0000000d
  66#define QE_ATM_MULTI_THREAD_INIT        0x00000011
  67#define QE_ASSIGN_PAGE                  0x00000012
  68#define QE_START_FLOW_CONTROL           0x00000014
  69#define QE_STOP_FLOW_CONTROL            0x00000015
  70#define QE_ASSIGN_PAGE_TO_DEVICE        0x00000016
  71#define QE_GRACEFUL_STOP_RX             0x0000001a
  72#define QE_RESTART_RX                   0x0000001b
  73
  74/* QE CECR Sub Block Code - sub block code of QE command.
  75*/
  76#define QE_CR_SUBBLOCK_INVALID          0x00000000
  77#define QE_CR_SUBBLOCK_USB              0x03200000
  78#define QE_CR_SUBBLOCK_UCCFAST1         0x02000000
  79#define QE_CR_SUBBLOCK_UCCFAST2         0x02200000
  80#define QE_CR_SUBBLOCK_UCCFAST3         0x02400000
  81#define QE_CR_SUBBLOCK_UCCFAST4         0x02600000
  82#define QE_CR_SUBBLOCK_UCCFAST5         0x02800000
  83#define QE_CR_SUBBLOCK_UCCFAST6         0x02a00000
  84#define QE_CR_SUBBLOCK_UCCFAST7         0x02c00000
  85#define QE_CR_SUBBLOCK_UCCFAST8         0x02e00000
  86#define QE_CR_SUBBLOCK_UCCSLOW1         0x00000000
  87#define QE_CR_SUBBLOCK_UCCSLOW2         0x00200000
  88#define QE_CR_SUBBLOCK_UCCSLOW3         0x00400000
  89#define QE_CR_SUBBLOCK_UCCSLOW4         0x00600000
  90#define QE_CR_SUBBLOCK_UCCSLOW5         0x00800000
  91#define QE_CR_SUBBLOCK_UCCSLOW6         0x00a00000
  92#define QE_CR_SUBBLOCK_UCCSLOW7         0x00c00000
  93#define QE_CR_SUBBLOCK_UCCSLOW8         0x00e00000
  94#define QE_CR_SUBBLOCK_MCC1             0x03800000
  95#define QE_CR_SUBBLOCK_MCC2             0x03a00000
  96#define QE_CR_SUBBLOCK_MCC3             0x03000000
  97#define QE_CR_SUBBLOCK_IDMA1            0x02800000
  98#define QE_CR_SUBBLOCK_IDMA2            0x02a00000
  99#define QE_CR_SUBBLOCK_IDMA3            0x02c00000
 100#define QE_CR_SUBBLOCK_IDMA4            0x02e00000
 101#define QE_CR_SUBBLOCK_HPAC             0x01e00000
 102#define QE_CR_SUBBLOCK_SPI1             0x01400000
 103#define QE_CR_SUBBLOCK_SPI2             0x01600000
 104#define QE_CR_SUBBLOCK_RAND             0x01c00000
 105#define QE_CR_SUBBLOCK_TIMER            0x01e00000
 106#define QE_CR_SUBBLOCK_GENERAL          0x03c00000
 107
 108/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
 109*/
 110#define QE_CR_PROTOCOL_UNSPECIFIED      0x00 /* For all other protocols */
 111#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
 112#define QE_CR_PROTOCOL_ATM_POS          0x0A
 113#define QE_CR_PROTOCOL_ETHERNET         0x0C
 114#define QE_CR_PROTOCOL_L2_SWITCH        0x0D
 115#define QE_CR_PROTOCOL_SHIFT            6
 116
 117/* QE ASSIGN PAGE command
 118*/
 119#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT    17
 120
 121/* Communication Direction.
 122*/
 123typedef enum comm_dir {
 124        COMM_DIR_NONE           = 0,
 125        COMM_DIR_RX             = 1,
 126        COMM_DIR_TX             = 2,
 127        COMM_DIR_RX_AND_TX      = 3
 128} comm_dir_e;
 129
 130/* Clocks and BRG's
 131*/
 132typedef enum qe_clock {
 133        QE_CLK_NONE = 0,
 134        QE_BRG1,     /* Baud Rate Generator  1 */
 135        QE_BRG2,     /* Baud Rate Generator  2 */
 136        QE_BRG3,     /* Baud Rate Generator  3 */
 137        QE_BRG4,     /* Baud Rate Generator  4 */
 138        QE_BRG5,     /* Baud Rate Generator  5 */
 139        QE_BRG6,     /* Baud Rate Generator  6 */
 140        QE_BRG7,     /* Baud Rate Generator  7 */
 141        QE_BRG8,     /* Baud Rate Generator  8 */
 142        QE_BRG9,     /* Baud Rate Generator  9 */
 143        QE_BRG10,    /* Baud Rate Generator 10 */
 144        QE_BRG11,    /* Baud Rate Generator 11 */
 145        QE_BRG12,    /* Baud Rate Generator 12 */
 146        QE_BRG13,    /* Baud Rate Generator 13 */
 147        QE_BRG14,    /* Baud Rate Generator 14 */
 148        QE_BRG15,    /* Baud Rate Generator 15 */
 149        QE_BRG16,    /* Baud Rate Generator 16 */
 150        QE_CLK1,     /* Clock  1               */
 151        QE_CLK2,     /* Clock  2               */
 152        QE_CLK3,     /* Clock  3               */
 153        QE_CLK4,     /* Clock  4               */
 154        QE_CLK5,     /* Clock  5               */
 155        QE_CLK6,     /* Clock  6               */
 156        QE_CLK7,     /* Clock  7               */
 157        QE_CLK8,     /* Clock  8               */
 158        QE_CLK9,     /* Clock  9               */
 159        QE_CLK10,    /* Clock 10               */
 160        QE_CLK11,    /* Clock 11               */
 161        QE_CLK12,    /* Clock 12               */
 162        QE_CLK13,    /* Clock 13               */
 163        QE_CLK14,    /* Clock 14               */
 164        QE_CLK15,    /* Clock 15               */
 165        QE_CLK16,    /* Clock 16               */
 166        QE_CLK17,    /* Clock 17               */
 167        QE_CLK18,    /* Clock 18               */
 168        QE_CLK19,    /* Clock 19               */
 169        QE_CLK20,    /* Clock 20               */
 170        QE_CLK21,    /* Clock 21               */
 171        QE_CLK22,    /* Clock 22               */
 172        QE_CLK23,    /* Clock 23               */
 173        QE_CLK24,    /* Clock 24               */
 174        QE_CLK_DUMMY
 175} qe_clock_e;
 176
 177/* QE CMXGCR register
 178*/
 179#define QE_CMXGCR_MII_ENET_MNG_MASK     0x00007000
 180#define QE_CMXGCR_MII_ENET_MNG_SHIFT    12
 181
 182/* QE CMXUCR registers
 183 */
 184#define QE_CMXUCR_TX_CLK_SRC_MASK       0x0000000F
 185
 186/* QE BRG configuration register
 187*/
 188#define QE_BRGC_ENABLE                  0x00010000
 189#define QE_BRGC_DIVISOR_SHIFT           1
 190#define QE_BRGC_DIVISOR_MAX             0xFFF
 191#define QE_BRGC_DIV16                   1
 192
 193/* QE SDMA registers
 194*/
 195#define QE_SDSR_BER1                    0x02000000
 196#define QE_SDSR_BER2                    0x01000000
 197
 198#define QE_SDMR_GLB_1_MSK               0x80000000
 199#define QE_SDMR_ADR_SEL                 0x20000000
 200#define QE_SDMR_BER1_MSK                0x02000000
 201#define QE_SDMR_BER2_MSK                0x01000000
 202#define QE_SDMR_EB1_MSK                 0x00800000
 203#define QE_SDMR_ER1_MSK                 0x00080000
 204#define QE_SDMR_ER2_MSK                 0x00040000
 205#define QE_SDMR_CEN_MASK                0x0000E000
 206#define QE_SDMR_SBER_1                  0x00000200
 207#define QE_SDMR_SBER_2                  0x00000200
 208#define QE_SDMR_EB1_PR_MASK             0x000000C0
 209#define QE_SDMR_ER1_PR                  0x00000008
 210
 211#define QE_SDMR_CEN_SHIFT               13
 212#define QE_SDMR_EB1_PR_SHIFT            6
 213
 214#define QE_SDTM_MSNUM_SHIFT             24
 215
 216#define QE_SDEBCR_BA_MASK               0x01FFFFFF
 217
 218/* Communication Processor */
 219#define QE_CP_CERCR_MEE         0x8000  /* Multi-user RAM ECC enable */
 220#define QE_CP_CERCR_IEE         0x4000  /* Instruction RAM ECC enable */
 221#define QE_CP_CERCR_CIR         0x0800  /* Common instruction RAM */
 222
 223/* I-RAM */
 224#define QE_IRAM_IADD_AIE        0x80000000      /* Auto Increment Enable */
 225#define QE_IRAM_IADD_BADDR      0x00080000      /* Base Address */
 226#define QE_IRAM_READY           0x80000000
 227
 228/* Structure that defines QE firmware binary files.
 229 *
 230 * See doc/README.qe_firmware for a description of these fields.
 231 */
 232struct qe_firmware {
 233        struct qe_header {
 234                u32 length;     /* Length of the entire structure, in bytes */
 235                u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
 236                u8 version;     /* Version of this layout. First ver is '1' */
 237        } header;
 238        u8 id[62];              /* Null-terminated identifier string */
 239        u8 split;               /* 0 = shared I-RAM, 1 = split I-RAM */
 240        u8 count;               /* Number of microcode[] structures */
 241        struct {
 242                u16 model;      /* The SOC model  */
 243                u8 major;       /* The SOC revision major */
 244                u8 minor;       /* The SOC revision minor */
 245        } __attribute__ ((packed)) soc;
 246        u8 padding[4];          /* Reserved, for alignment */
 247        u64 extended_modes;     /* Extended modes */
 248        u32 vtraps[8];          /* Virtual trap addresses */
 249        u8 reserved[4];         /* Reserved, for future expansion */
 250        struct qe_microcode {
 251                u8 id[32];      /* Null-terminated identifier */
 252                u32 traps[16];  /* Trap addresses, 0 == ignore */
 253                u32 eccr;       /* The value for the ECCR register */
 254                u32 iram_offset;/* Offset into I-RAM for the code */
 255                u32 count;      /* Number of 32-bit words of the code */
 256                u32 code_offset;/* Offset of the actual microcode */
 257                u8 major;       /* The microcode version major */
 258                u8 minor;       /* The microcode version minor */
 259                u8 revision;    /* The microcode version revision */
 260                u8 padding;     /* Reserved, for alignment */
 261                u8 reserved[4]; /* Reserved, for future expansion */
 262        } __attribute__ ((packed)) microcode[1];
 263        /* All microcode binaries should be located here */
 264        /* CRC32 should be located here, after the microcode binaries */
 265} __attribute__ ((packed));
 266
 267struct qe_firmware_info {
 268        char id[64];            /* Firmware name */
 269        u32 vtraps[8];          /* Virtual trap addresses */
 270        u64 extended_modes;     /* Extended modes */
 271};
 272
 273void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
 274void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
 275uint qe_muram_alloc(uint size, uint align);
 276void *qe_muram_addr(uint offset);
 277int qe_get_snum(void);
 278void qe_put_snum(u8 snum);
 279void qe_init(uint qe_base);
 280void qe_reset(void);
 281void qe_assign_page(uint snum, uint para_ram_base);
 282int qe_set_brg(uint brg, uint rate);
 283int qe_set_mii_clk_src(int ucc_num);
 284int qe_upload_firmware(const struct qe_firmware *firmware);
 285struct qe_firmware_info *qe_get_firmware_info(void);
 286void ft_qe_setup(void *blob);
 287void qe_init(uint qe_base);
 288void qe_reset(void);
 289
 290#ifdef CONFIG_U_QE
 291void u_qe_init(void);
 292int u_qe_upload_firmware(const struct qe_firmware *firmware);
 293void u_qe_resume(void);
 294int u_qe_firmware_resume(const struct qe_firmware *firmware,
 295                         qe_map_t *qe_immrr);
 296#endif
 297
 298#endif /* __QE_H__ */
 299