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8#ifndef _MEM_H_
9#define _MEM_H_
10
11#define CS0 0x0
12#define CS1 0x1
13
14#ifndef __ASSEMBLY__
15enum {
16 STACKED = 0,
17 IP_DDR = 1,
18 COMBO_DDR = 2,
19 IP_SDR = 3,
20};
21#endif
22
23#define EARLY_INIT 1
24
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30
31
32#define SDRC_SHARING 0x00000100
33#define SDRC_MR_0_SDR 0x00000031
34
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38
39
40#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
41#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01
42#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201
43#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601
44
45#define DLL_OFFSET 0
46#define DLL_WRITEDDRCLKX2DIS 1
47#define DLL_ENADLL 1
48#define DLL_LOCKDLL 0
49#define DLL_DLLPHASE_72 0
50#define DLL_DLLPHASE_90 1
51
52
53#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
54 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
55
56
57#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27)
58#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22)
59#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18)
60#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15)
61#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12)
62#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9)
63#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6)
64#define ACTIM_CTRLA_TDAL(v) (v & 0x1F)
65
66#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \
67 ACTIM_CTRLA_TRFC(trfc) | \
68 ACTIM_CTRLA_TRC(trc) | \
69 ACTIM_CTRLA_TRAS(tras) | \
70 ACTIM_CTRLA_TRP(trp) | \
71 ACTIM_CTRLA_TRCD(trcd) | \
72 ACTIM_CTRLA_TRRD(trrd) | \
73 ACTIM_CTRLA_TDPL(tdpl) | \
74 ACTIM_CTRLA_TDAL(tdal)
75
76
77#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16)
78#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12)
79#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8)
80#define ACTIM_CTRLB_TXSR(v) (v & 0xFF)
81
82#define ACTIM_CTRLB(twtr, tcke, txp, txsr) \
83 ACTIM_CTRLB_TWTR(twtr) | \
84 ACTIM_CTRLB_TCKE(tcke) | \
85 ACTIM_CTRLB_TXP(txp) | \
86 ACTIM_CTRLB_TXSR(txsr)
87
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91
92
93#define V_MCFG_RAMTYPE_DDR (0x1)
94#define V_MCFG_DEEPPD_EN (0x1 << 3)
95#define V_MCFG_B32NOT16_32 (0x1 << 4)
96#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6)
97#define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8)
98#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19)
99#define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20)
100#define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10)
101#define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24)
102
103
104#define MCFG(ramsize, raswidth) \
105 V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B | \
106 V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) | \
107 V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 | \
108 V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
109
110
111#define HYNIX_TDAL_165 6
112#define HYNIX_TDPL_165 3
113#define HYNIX_TRRD_165 2
114#define HYNIX_TRCD_165 3
115#define HYNIX_TRP_165 3
116#define HYNIX_TRAS_165 7
117#define HYNIX_TRC_165 10
118#define HYNIX_TRFC_165 21
119#define HYNIX_V_ACTIMA_165 \
120 ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \
121 HYNIX_TRAS_165, HYNIX_TRP_165, \
122 HYNIX_TRCD_165, HYNIX_TRRD_165, \
123 HYNIX_TDPL_165, HYNIX_TDAL_165)
124
125#define HYNIX_TWTR_165 1
126#define HYNIX_TCKE_165 1
127#define HYNIX_TXP_165 2
128#define HYNIX_XSR_165 24
129#define HYNIX_V_ACTIMB_165 \
130 ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \
131 HYNIX_TXP_165, HYNIX_XSR_165)
132
133#define HYNIX_RASWIDTH_165 13
134#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165)
135
136
137#define HYNIX_TDAL_200 6
138#define HYNIX_TDPL_200 3
139#define HYNIX_TRRD_200 2
140#define HYNIX_TRCD_200 4
141#define HYNIX_TRP_200 3
142#define HYNIX_TRAS_200 8
143#define HYNIX_TRC_200 11
144#define HYNIX_TRFC_200 18
145#define HYNIX_V_ACTIMA_200 \
146 ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
147 HYNIX_TRAS_200, HYNIX_TRP_200, \
148 HYNIX_TRCD_200, HYNIX_TRRD_200, \
149 HYNIX_TDPL_200, HYNIX_TDAL_200)
150
151#define HYNIX_TWTR_200 2
152#define HYNIX_TCKE_200 1
153#define HYNIX_TXP_200 1
154#define HYNIX_XSR_200 28
155#define HYNIX_V_ACTIMB_200 \
156 ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
157 HYNIX_TXP_200, HYNIX_XSR_200)
158
159#define HYNIX_RASWIDTH_200 14
160#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
161
162
163#define INFINEON_TDAL_165 6
164
165#define INFINEON_TDPL_165 3
166#define INFINEON_TRRD_165 2
167#define INFINEON_TRCD_165 3
168#define INFINEON_TRP_165 3
169#define INFINEON_TRAS_165 7
170#define INFINEON_TRC_165 10
171#define INFINEON_TRFC_165 12
172
173#define INFINEON_V_ACTIMA_165 \
174 ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \
175 INFINEON_TRAS_165, INFINEON_TRP_165, \
176 INFINEON_TRCD_165, INFINEON_TRRD_165, \
177 INFINEON_TDPL_165, INFINEON_TDAL_165)
178
179#define INFINEON_TWTR_165 1
180#define INFINEON_TCKE_165 2
181#define INFINEON_TXP_165 2
182#define INFINEON_XSR_165 20
183
184#define INFINEON_V_ACTIMB_165 \
185 ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \
186 INFINEON_TXP_165, INFINEON_XSR_165)
187
188
189#define MICRON_TDAL_165 6
190
191#define MICRON_TDPL_165 3
192#define MICRON_TRRD_165 2
193#define MICRON_TRCD_165 3
194#define MICRON_TRP_165 3
195#define MICRON_TRAS_165 7
196#define MICRON_TRC_165 10
197#define MICRON_TRFC_165 21
198
199#define MICRON_V_ACTIMA_165 \
200 ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \
201 MICRON_TRAS_165, MICRON_TRP_165, \
202 MICRON_TRCD_165, MICRON_TRRD_165, \
203 MICRON_TDPL_165, MICRON_TDAL_165)
204
205#define MICRON_TWTR_165 1
206#define MICRON_TCKE_165 1
207#define MICRON_XSR_165 23
208#define MICRON_TXP_165 5
209
210#define MICRON_V_ACTIMB_165 \
211 ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
212 MICRON_TXP_165, MICRON_XSR_165)
213
214#define MICRON_RASWIDTH_165 13
215#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165)
216
217#define MICRON_BL_165 0x2
218#define MICRON_SIL_165 0x0
219#define MICRON_CASL_165 0x3
220#define MICRON_WBST_165 0x0
221#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \
222 (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
223 (MICRON_BL_165))
224
225
226#define MICRON_TDAL_200 6
227#define MICRON_TDPL_200 3
228#define MICRON_TRRD_200 2
229#define MICRON_TRCD_200 3
230#define MICRON_TRP_200 3
231#define MICRON_TRAS_200 8
232#define MICRON_TRC_200 11
233#define MICRON_TRFC_200 15
234#define MICRON_V_ACTIMA_200 \
235 ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \
236 MICRON_TRAS_200, MICRON_TRP_200, \
237 MICRON_TRCD_200, MICRON_TRRD_200, \
238 MICRON_TDPL_200, MICRON_TDAL_200)
239
240#define MICRON_TWTR_200 2
241#define MICRON_TCKE_200 4
242#define MICRON_TXP_200 2
243#define MICRON_XSR_200 23
244#define MICRON_V_ACTIMB_200 \
245 ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \
246 MICRON_TXP_200, MICRON_XSR_200)
247
248#define MICRON_RASWIDTH_200 14
249#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
250
251
252#define SAMSUNG_TDAL_165 5
253#define SAMSUNG_TDPL_165 2
254#define SAMSUNG_TRRD_165 2
255#define SAMSUNG_TRCD_165 3
256#define SAMSUNG_TRP_165 3
257#define SAMSUNG_TRAS_165 7
258#define SAMSUNG_TRC_165 10
259#define SAMSUNG_TRFC_165 12
260
261#define SAMSUNG_V_ACTIMA_165 \
262 ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \
263 SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \
264 SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \
265 SAMSUNG_TDPL_165, SAMSUNG_TDAL_165)
266
267#define SAMSUNG_TWTR_165 1
268#define SAMSUNG_TCKE_165 2
269#define SAMSUNG_XSR_165 20
270#define SAMSUNG_TXP_165 5
271
272#define SAMSUNG_V_ACTIMB_165 \
273 ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \
274 SAMSUNG_TXP_165, SAMSUNG_XSR_165)
275
276#define SAMSUNG_RASWIDTH_165 14
277#define SAMSUNG_V_MCFG_165(size) \
278 V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \
279 V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \
280 V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR
281
282
283
284#define SAMSUNG_BL_165 0x2
285#define SAMSUNG_SIL_165 0x0
286#define SAMSUNG_CASL_165 0x3
287#define SAMSUNG_WBST_165 0x0
288#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \
289 (SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \
290 (SAMSUNG_BL_165))
291
292#define SAMSUNG_SHARING 0x00003700
293
294
295#define NUMONYX_TDAL_165 6
296
297#define NUMONYX_TDPL_165 3
298#define NUMONYX_TRRD_165 2
299#define NUMONYX_TRCD_165 4
300#define NUMONYX_TRP_165 3
301#define NUMONYX_TRAS_165 7
302#define NUMONYX_TRC_165 10
303#define NUMONYX_TRFC_165 24
304
305#define NUMONYX_V_ACTIMA_165 \
306 ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \
307 NUMONYX_TRAS_165, NUMONYX_TRP_165, \
308 NUMONYX_TRCD_165, NUMONYX_TRRD_165, \
309 NUMONYX_TDPL_165, NUMONYX_TDAL_165)
310
311#define NUMONYX_TWTR_165 2
312#define NUMONYX_TCKE_165 2
313#define NUMONYX_TXP_165 3
314#define NUMONYX_XSR_165 34
315
316#define NUMONYX_V_ACTIMB_165 \
317 ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
318 NUMONYX_TXP_165, NUMONYX_XSR_165)
319
320#define NUMONYX_RASWIDTH_165 15
321#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
322
323
324#define NUMONYX_TDAL_200 6
325
326#define NUMONYX_TDPL_200 3
327#define NUMONYX_TRRD_200 2
328#define NUMONYX_TRCD_200 4
329#define NUMONYX_TRP_200 3
330#define NUMONYX_TRAS_200 8
331#define NUMONYX_TRC_200 11
332#define NUMONYX_TRFC_200 28
333
334#define NUMONYX_V_ACTIMA_200 \
335 ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \
336 NUMONYX_TRAS_200, NUMONYX_TRP_200, \
337 NUMONYX_TRCD_200, NUMONYX_TRRD_200, \
338 NUMONYX_TDPL_200, NUMONYX_TDAL_200)
339
340#define NUMONYX_TWTR_200 2
341#define NUMONYX_TCKE_200 2
342#define NUMONYX_TXP_200 3
343#define NUMONYX_XSR_200 40
344
345#define NUMONYX_V_ACTIMB_200 \
346 ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \
347 NUMONYX_TXP_200, NUMONYX_XSR_200)
348
349#define NUMONYX_RASWIDTH_200 15
350#define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200)
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389#define GPMC_SIZE_256M 0x0
390#define GPMC_SIZE_128M 0x8
391#define GPMC_SIZE_64M 0xC
392#define GPMC_SIZE_32M 0xE
393#define GPMC_SIZE_16M 0xF
394
395#define GPMC_BASEADDR_MASK 0x3F
396
397#define GPMC_CS_ENABLE 0x1
398
399#define M_NAND_GPMC_CONFIG1 0x00001800
400#define M_NAND_GPMC_CONFIG2 0x00141400
401#define M_NAND_GPMC_CONFIG3 0x00141400
402#define M_NAND_GPMC_CONFIG4 0x0F010F01
403#define M_NAND_GPMC_CONFIG5 0x010C1414
404#define M_NAND_GPMC_CONFIG6 0x1f0f0A80
405#define M_NAND_GPMC_CONFIG7 0x00000C44
406
407#define STNOR_GPMC_CONFIG1 0x3
408#define STNOR_GPMC_CONFIG2 0x00151501
409#define STNOR_GPMC_CONFIG3 0x00060602
410#define STNOR_GPMC_CONFIG4 0x11091109
411#define STNOR_GPMC_CONFIG5 0x01141F1F
412#define STNOR_GPMC_CONFIG6 0x000004c4
413
414#define SIBNOR_GPMC_CONFIG1 0x1200
415#define SIBNOR_GPMC_CONFIG2 0x001f1f00
416#define SIBNOR_GPMC_CONFIG3 0x00080802
417#define SIBNOR_GPMC_CONFIG4 0x1C091C09
418#define SIBNOR_GPMC_CONFIG5 0x01131F1F
419#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
420
421#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
422#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
423#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
424#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
425#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
426#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
427
428#define MPDB_GPMC_CONFIG1 0x00011000
429#define MPDB_GPMC_CONFIG2 0x001f1f01
430#define MPDB_GPMC_CONFIG3 0x00080803
431#define MPDB_GPMC_CONFIG4 0x1c0b1c0a
432#define MPDB_GPMC_CONFIG5 0x041f1F1F
433#define MPDB_GPMC_CONFIG6 0x1F0F04C4
434
435#define P2_GPMC_CONFIG1 0x0
436#define P2_GPMC_CONFIG2 0x0
437#define P2_GPMC_CONFIG3 0x0
438#define P2_GPMC_CONFIG4 0x0
439#define P2_GPMC_CONFIG5 0x0
440#define P2_GPMC_CONFIG6 0x0
441
442#define ONENAND_GPMC_CONFIG1 0x00001200
443#define ONENAND_GPMC_CONFIG2 0x000F0F01
444#define ONENAND_GPMC_CONFIG3 0x00030301
445#define ONENAND_GPMC_CONFIG4 0x0F040F04
446#define ONENAND_GPMC_CONFIG5 0x010F1010
447#define ONENAND_GPMC_CONFIG6 0x1F060000
448
449#define NET_GPMC_CONFIG1 0x00001000
450#define NET_GPMC_CONFIG2 0x001e1e01
451#define NET_GPMC_CONFIG3 0x00080300
452#define NET_GPMC_CONFIG4 0x1c091c09
453#define NET_GPMC_CONFIG5 0x04181f1f
454#define NET_GPMC_CONFIG6 0x00000FCF
455#define NET_GPMC_CONFIG7 0x00000f6c
456
457
458#define NET_LAN9221_GPMC_CONFIG1 0x00001000
459#define NET_LAN9221_GPMC_CONFIG2 0x00060700
460#define NET_LAN9221_GPMC_CONFIG3 0x00020201
461#define NET_LAN9221_GPMC_CONFIG4 0x06000700
462#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
463#define NET_LAN9221_GPMC_CONFIG6 0x87030000
464#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
465
466
467
468#define GPMC_MAX_CS 8
469
470#define GPMC_MAX_REG 7
471
472#define DBG_MPDB 6
473#define DBG_MPDB_BASE DEBUG_BASE
474
475#ifndef __ASSEMBLY__
476
477
478void mem_init(void);
479
480u32 is_mem_sdr(void);
481u32 mem_ok(u32 cs);
482
483u32 get_sdr_cs_size(u32);
484u32 get_sdr_cs_offset(u32);
485
486#endif
487
488#endif
489