1
2
3
4
5#ifndef _ASM_ARCH_SDRAM_RK322X_H
6#define _ASM_ARCH_SDRAM_RK322X_H
7
8#include <common.h>
9
10struct rk322x_sdram_channel {
11
12
13
14
15
16 u8 rank;
17 u8 col;
18 u8 bk;
19 u8 bw;
20 u8 dbw;
21 u8 row_3_4;
22 u8 cs0_row;
23 u8 cs1_row;
24#if CONFIG_IS_ENABLED(OF_PLATDATA)
25
26
27
28
29
30
31
32 u8 dummy;
33#endif
34};
35
36struct rk322x_ddr_pctl {
37 u32 scfg;
38 u32 sctl;
39 u32 stat;
40 u32 intrstat;
41 u32 reserved0[(0x40 - 0x10) / 4];
42 u32 mcmd;
43 u32 powctl;
44 u32 powstat;
45 u32 cmdtstat;
46 u32 cmdtstaten;
47 u32 reserved1[(0x60 - 0x54) / 4];
48 u32 mrrcfg0;
49 u32 mrrstat0;
50 u32 mrrstat1;
51 u32 reserved2[(0x7c - 0x6c) / 4];
52
53 u32 mcfg1;
54 u32 mcfg;
55 u32 ppcfg;
56 u32 mstat;
57 u32 lpddr2zqcfg;
58 u32 reserved3;
59
60 u32 dtupdes;
61 u32 dtuna;
62 u32 dtune;
63 u32 dtuprd0;
64 u32 dtuprd1;
65 u32 dtuprd2;
66 u32 dtuprd3;
67 u32 dtuawdt;
68 u32 reserved4[(0xc0 - 0xb4) / 4];
69
70 u32 togcnt1u;
71 u32 tinit;
72 u32 trsth;
73 u32 togcnt100n;
74 u32 trefi;
75 u32 tmrd;
76 u32 trfc;
77 u32 trp;
78 u32 trtw;
79 u32 tal;
80 u32 tcl;
81 u32 tcwl;
82 u32 tras;
83 u32 trc;
84 u32 trcd;
85 u32 trrd;
86 u32 trtp;
87 u32 twr;
88 u32 twtr;
89 u32 texsr;
90 u32 txp;
91 u32 txpdll;
92 u32 tzqcs;
93 u32 tzqcsi;
94 u32 tdqs;
95 u32 tcksre;
96 u32 tcksrx;
97 u32 tcke;
98 u32 tmod;
99 u32 trstl;
100 u32 tzqcl;
101 u32 tmrr;
102 u32 tckesr;
103 u32 tdpd;
104 u32 tref_mem_ddr3;
105 u32 reserved5[(0x180 - 0x14c) / 4];
106 u32 ecccfg;
107 u32 ecctst;
108 u32 eccclr;
109 u32 ecclog;
110 u32 reserved6[(0x200 - 0x190) / 4];
111 u32 dtuwactl;
112 u32 dturactl;
113 u32 dtucfg;
114 u32 dtuectl;
115 u32 dtuwd0;
116 u32 dtuwd1;
117 u32 dtuwd2;
118 u32 dtuwd3;
119 u32 dtuwdm;
120 u32 dturd0;
121 u32 dturd1;
122 u32 dturd2;
123 u32 dturd3;
124 u32 dtulfsrwd;
125 u32 dtulfsrrd;
126 u32 dtueaf;
127
128 u32 dfitctrldelay;
129 u32 dfiodtcfg;
130 u32 dfiodtcfg1;
131 u32 dfiodtrankmap;
132
133 u32 dfitphywrdata;
134 u32 dfitphywrlat;
135 u32 reserved7[(0x260 - 0x258) / 4];
136 u32 dfitrddataen;
137 u32 dfitphyrdlat;
138 u32 reserved8[(0x270 - 0x268) / 4];
139 u32 dfitphyupdtype0;
140 u32 dfitphyupdtype1;
141 u32 dfitphyupdtype2;
142 u32 dfitphyupdtype3;
143 u32 dfitctrlupdmin;
144 u32 dfitctrlupdmax;
145 u32 dfitctrlupddly;
146 u32 reserved9;
147 u32 dfiupdcfg;
148 u32 dfitrefmski;
149 u32 dfitctrlupdi;
150 u32 reserved10[(0x2ac - 0x29c) / 4];
151 u32 dfitrcfg0;
152 u32 dfitrstat0;
153 u32 dfitrwrlvlen;
154 u32 dfitrrdlvlen;
155 u32 dfitrrdlvlgateen;
156 u32 dfiststat0;
157 u32 dfistcfg0;
158 u32 dfistcfg1;
159 u32 reserved11;
160 u32 dfitdramclken;
161 u32 dfitdramclkdis;
162 u32 dfistcfg2;
163 u32 dfistparclr;
164 u32 dfistparlog;
165 u32 reserved12[(0x2f0 - 0x2e4) / 4];
166
167 u32 dfilpcfg0;
168 u32 reserved13[(0x300 - 0x2f4) / 4];
169 u32 dfitrwrlvlresp0;
170 u32 dfitrwrlvlresp1;
171 u32 dfitrwrlvlresp2;
172 u32 dfitrrdlvlresp0;
173 u32 dfitrrdlvlresp1;
174 u32 dfitrrdlvlresp2;
175 u32 dfitrwrlvldelay0;
176 u32 dfitrwrlvldelay1;
177 u32 dfitrwrlvldelay2;
178 u32 dfitrrdlvldelay0;
179 u32 dfitrrdlvldelay1;
180 u32 dfitrrdlvldelay2;
181 u32 dfitrrdlvlgatedelay0;
182 u32 dfitrrdlvlgatedelay1;
183 u32 dfitrrdlvlgatedelay2;
184 u32 dfitrcmd;
185 u32 reserved14[(0x3f8 - 0x340) / 4];
186 u32 ipvr;
187 u32 iptr;
188};
189check_member(rk322x_ddr_pctl, iptr, 0x03fc);
190
191struct rk322x_ddr_phy {
192 u32 ddrphy_reg[0x100];
193};
194
195struct rk322x_pctl_timing {
196 u32 togcnt1u;
197 u32 tinit;
198 u32 trsth;
199 u32 togcnt100n;
200 u32 trefi;
201 u32 tmrd;
202 u32 trfc;
203 u32 trp;
204 u32 trtw;
205 u32 tal;
206 u32 tcl;
207 u32 tcwl;
208 u32 tras;
209 u32 trc;
210 u32 trcd;
211 u32 trrd;
212 u32 trtp;
213 u32 twr;
214 u32 twtr;
215 u32 texsr;
216 u32 txp;
217 u32 txpdll;
218 u32 tzqcs;
219 u32 tzqcsi;
220 u32 tdqs;
221 u32 tcksre;
222 u32 tcksrx;
223 u32 tcke;
224 u32 tmod;
225 u32 trstl;
226 u32 tzqcl;
227 u32 tmrr;
228 u32 tckesr;
229 u32 tdpd;
230 u32 trefi_mem_ddr3;
231};
232
233struct rk322x_phy_timing {
234 u32 mr[4];
235 u32 mr11;
236 u32 bl;
237 u32 cl_al;
238};
239
240struct rk322x_msch_timings {
241 u32 ddrtiming;
242 u32 ddrmode;
243 u32 readlatency;
244 u32 activate;
245 u32 devtodev;
246};
247
248struct rk322x_service_sys {
249 u32 id_coreid;
250 u32 id_revisionid;
251 u32 ddrconf;
252 u32 ddrtiming;
253 u32 ddrmode;
254 u32 readlatency;
255 u32 activate;
256 u32 devtodev;
257};
258
259struct rk322x_base_params {
260 struct rk322x_msch_timings noc_timing;
261 u32 ddrconfig;
262 u32 ddr_freq;
263 u32 dramtype;
264
265
266
267 u32 stride;
268 u32 odt;
269};
270
271
272#define DFI_INIT_START BIT(0)
273#define DFI_DATA_BYTE_DISABLE_EN BIT(2)
274
275
276#define DFI_DRAM_CLK_SR_EN BIT(0)
277#define DFI_DRAM_CLK_DPD_EN BIT(1)
278
279
280#define DFI_PARITY_INTR_EN BIT(0)
281#define DFI_PARITY_EN BIT(1)
282
283
284#define TLP_RESP_TIME_SHIFT 16
285#define LP_SR_EN BIT(8)
286#define LP_PD_EN BIT(0)
287
288
289#define TCTRL_DELAY_TIME_SHIFT 0
290
291
292#define TPHY_WRDATA_TIME_SHIFT 0
293
294
295#define TPHY_RDLAT_TIME_SHIFT 0
296
297
298#define TDRAM_CLK_DIS_TIME_SHIFT 0
299
300
301#define TDRAM_CLK_EN_TIME_SHIFT 0
302
303
304#define RANK0_ODT_WRITE_SEL BIT(3)
305#define RANK1_ODT_WRITE_SEL BIT(11)
306
307
308#define ODT_LEN_BL8_W_SHIFT 16
309
310
311#define ACDLLCR_DLLDIS BIT(31)
312#define ACDLLCR_DLLSRST BIT(30)
313
314
315#define DXDLLCR_DLLDIS BIT(31)
316#define DXDLLCR_DLLSRST BIT(30)
317
318
319#define DLLGCR_SBIAS BIT(30)
320
321
322#define DQSRTT BIT(9)
323#define DQRTT BIT(10)
324
325
326#define PIR_INIT BIT(0)
327#define PIR_DLLSRST BIT(1)
328#define PIR_DLLLOCK BIT(2)
329#define PIR_ZCAL BIT(3)
330#define PIR_ITMSRST BIT(4)
331#define PIR_DRAMRST BIT(5)
332#define PIR_DRAMINIT BIT(6)
333#define PIR_QSTRN BIT(7)
334#define PIR_RVTRN BIT(8)
335#define PIR_ICPC BIT(16)
336#define PIR_DLLBYP BIT(17)
337#define PIR_CTLDINIT BIT(18)
338#define PIR_CLRSR BIT(28)
339#define PIR_LOCKBYP BIT(29)
340#define PIR_ZCALBYP BIT(30)
341#define PIR_INITBYP BIT(31)
342
343
344#define PGCR_DFTLMT_SHIFT 3
345#define PGCR_DFTCMP_SHIFT 2
346#define PGCR_DQSCFG_SHIFT 1
347#define PGCR_ITMDMD_SHIFT 0
348
349
350#define PGSR_IDONE BIT(0)
351#define PGSR_DLDONE BIT(1)
352#define PGSR_ZCDONE BIT(2)
353#define PGSR_DIDONE BIT(3)
354#define PGSR_DTDONE BIT(4)
355#define PGSR_DTERR BIT(5)
356#define PGSR_DTIERR BIT(6)
357#define PGSR_DFTERR BIT(7)
358#define PGSR_RVERR BIT(8)
359#define PGSR_RVEIRR BIT(9)
360
361
362#define PRT_ITMSRST_SHIFT 18
363#define PRT_DLLLOCK_SHIFT 6
364#define PRT_DLLSRST_SHIFT 0
365
366
367#define PRT_DINIT0_SHIFT 0
368#define PRT_DINIT1_SHIFT 19
369
370
371#define PRT_DINIT2_SHIFT 0
372#define PRT_DINIT3_SHIFT 17
373
374
375#define DDRMD_LPDDR 0
376#define DDRMD_DDR 1
377#define DDRMD_DDR2 2
378#define DDRMD_DDR3 3
379#define DDRMD_LPDDR2_LPDDR3 4
380#define DDRMD_MASK 7
381#define DDRMD_SHIFT 0
382#define PDQ_MASK 7
383#define PDQ_SHIFT 4
384
385
386#define DQSNRES_MASK 0xf
387#define DQSNRES_SHIFT 8
388#define DQSRES_MASK 0xf
389#define DQSRES_SHIFT 4
390
391
392#define TDQSCKMAX_SHIFT 27
393#define TDQSCKMAX_MASK 7
394#define TDQSCK_SHIFT 24
395#define TDQSCK_MASK 7
396
397
398#define DQSGX_SHIFT 5
399#define DQSGX_MASK 7
400#define DQSGE_SHIFT 8
401#define DQSGE_MASK 7
402
403
404#define INIT_STATE 0
405#define CFG_STATE 1
406#define GO_STATE 2
407#define SLEEP_STATE 3
408#define WAKEUP_STATE 4
409
410
411#define LP_TRIG_SHIFT 4
412#define LP_TRIG_MASK 7
413#define PCTL_STAT_MASK 7
414#define INIT_MEM 0
415#define CONFIG 1
416#define CONFIG_REQ 2
417#define ACCESS 3
418#define ACCESS_REQ 4
419#define LOW_POWER 5
420#define LOW_POWER_ENTRY_REQ 6
421#define LOW_POWER_EXIT_REQ 7
422
423
424#define PD_OUTPUT_SHIFT 0
425#define PU_OUTPUT_SHIFT 5
426#define PD_ONDIE_SHIFT 10
427#define PU_ONDIE_SHIFT 15
428#define ZDEN_SHIFT 28
429
430
431#define SBIAS_BYPASS BIT(23)
432
433
434#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24
435#define PD_IDLE_SHIFT 8
436#define MDDR_EN (2 << 22)
437#define LPDDR2_EN (3 << 22)
438#define LPDDR3_EN (1 << 22)
439#define DDR2_EN (0 << 5)
440#define DDR3_EN (1 << 5)
441#define LPDDR2_S2 (0 << 6)
442#define LPDDR2_S4 (1 << 6)
443#define MDDR_LPDDR2_BL_2 (0 << 20)
444#define MDDR_LPDDR2_BL_4 (1 << 20)
445#define MDDR_LPDDR2_BL_8 (2 << 20)
446#define MDDR_LPDDR2_BL_16 (3 << 20)
447#define DDR2_DDR3_BL_4 0
448#define DDR2_DDR3_BL_8 1
449#define TFAW_SHIFT 18
450#define PD_EXIT_SLOW (0 << 17)
451#define PD_EXIT_FAST (1 << 17)
452#define PD_TYPE_SHIFT 16
453#define BURSTLENGTH_SHIFT 20
454
455
456#define POWER_UP_START BIT(0)
457
458
459#define POWER_UP_DONE BIT(0)
460
461
462enum {
463 DESELECT_CMD = 0,
464 PREA_CMD,
465 REF_CMD,
466 MRS_CMD,
467 ZQCS_CMD,
468 ZQCL_CMD,
469 RSTL_CMD,
470 MRR_CMD = 8,
471 DPDE_CMD,
472};
473
474#define BANK_ADDR_MASK 7
475#define BANK_ADDR_SHIFT 17
476#define CMD_ADDR_MASK 0x1fff
477#define CMD_ADDR_SHIFT 4
478
479#define LPDDR23_MA_SHIFT 4
480#define LPDDR23_MA_MASK 0xff
481#define LPDDR23_OP_SHIFT 12
482#define LPDDR23_OP_MASK 0xff
483
484#define START_CMD (1u << 31)
485
486
487enum {
488
489 SOFT_RESET_MASK = 3,
490 SOFT_DERESET_ANALOG = 1 << 2,
491 SOFT_DERESET_DIGITAL = 1 << 3,
492 SOFT_RESET_SHIFT = 2,
493
494
495 PHY_DDR3 = 0,
496 PHY_DDR2 = 1,
497 PHY_LPDDR3 = 2,
498 PHY_LPDDR2 = 3,
499
500 PHT_BL_8 = 1 << 2,
501 PHY_BL_4 = 0 << 2,
502
503
504 MEMORY_SELECT_DDR3 = 0 << 0,
505 MEMORY_SELECT_LPDDR3 = 2 << 0,
506 MEMORY_SELECT_LPDDR2 = 3 << 0,
507 DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4,
508 DQS_SQU_CAL_SEL_CS1 = 1 << 4,
509 DQS_SQU_CAL_SEL_CS0 = 2 << 4,
510 DQS_SQU_CAL_NORMAL_MODE = 0 << 1,
511 DQS_SQU_CAL_BYPASS_MODE = 1 << 1,
512 DQS_SQU_CAL_START = 1 << 0,
513 DQS_SQU_NO_CAL = 0 << 0,
514};
515
516
517enum {
518 PHY_RON_RTT_DISABLE = 0,
519 PHY_RON_RTT_451OHM = 1,
520 PHY_RON_RTT_225OHM,
521 PHY_RON_RTT_150OHM,
522 PHY_RON_RTT_112OHM,
523 PHY_RON_RTT_90OHM,
524 PHY_RON_RTT_75OHM,
525 PHY_RON_RTT_64OHM = 7,
526
527 PHY_RON_RTT_56OHM = 16,
528 PHY_RON_RTT_50OHM,
529 PHY_RON_RTT_45OHM,
530 PHY_RON_RTT_41OHM,
531 PHY_RON_RTT_37OHM,
532 PHY_RON_RTT_34OHM,
533 PHY_RON_RTT_33OHM,
534 PHY_RON_RTT_30OHM = 23,
535
536 PHY_RON_RTT_28OHM = 24,
537 PHY_RON_RTT_26OHM,
538 PHY_RON_RTT_25OHM,
539 PHY_RON_RTT_23OHM,
540 PHY_RON_RTT_22OHM,
541 PHY_RON_RTT_21OHM,
542 PHY_RON_RTT_20OHM,
543 PHY_RON_RTT_19OHM = 31,
544};
545
546
547enum {
548 DQS_DLL_NO_DELAY = 0,
549 DQS_DLL_22P5_DELAY,
550 DQS_DLL_45_DELAY,
551 DQS_DLL_67P5_DELAY,
552 DQS_DLL_90_DELAY,
553 DQS_DLL_112P5_DELAY,
554 DQS_DLL_135_DELAY,
555 DQS_DLL_157P5_DELAY,
556};
557
558
559#define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0))
560#define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0))
561#define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7))
562#define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7))
563
564#define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8))
565#define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8))
566
567#define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6))
568#define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6))
569
570#define PHY_DRV_ODT_SET(n) (((n) << 4) | (n))
571#define DDR3_DLL_RESET (1 << 8)
572
573#endif
574
