LXR uboot/arch/arm/mach-meson/board-axg.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
   4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
   5 */
   6
   7#include <common.h>
   8#include <asm/arch/boot.h>
   9#include <asm/arch/eth.h>
  10#include <asm/arch/axg.h>
  11#include <asm/arch/mem.h>
  12#include <asm/io.h>
  13#include <asm/armv8/mmu.h>
  14#include <linux/sizes.h>
  15#include <phy.h>
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19int meson_get_boot_device(void)
  20{
  21        return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
  22}
  23
  24/* Configure the reserved memory zones exported by the secure registers
  25 * into EFI and DTB reserved memory entries.
  26 */
  27void meson_init_reserved_memory(void *fdt)
  28{
  29        u64 bl31_size, bl31_start;
  30        u64 bl32_size, bl32_start;
  31        u32 reg;
  32
  33        /*
  34         * Get ARM Trusted Firmware reserved memory zones in :
  35         * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  36         * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  37         * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  38         */
  39        reg = readl(AXG_AO_SEC_GP_CFG3);
  40
  41        bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
  42                        >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  43        bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  44
  45        bl31_start = readl(AXG_AO_SEC_GP_CFG5);
  46        bl32_start = readl(AXG_AO_SEC_GP_CFG4);
  47
  48        /* Add BL31 reserved zone */
  49        if (bl31_start && bl31_size)
  50                meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  51
  52        /* Add BL32 reserved zone */
  53        if (bl32_start && bl32_size)
  54                meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  55}
  56
  57phys_size_t get_effective_memsize(void)
  58{
  59        /* Size is reported in MiB, convert it in bytes */
  60        return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
  61                        >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
  62}
  63
  64static struct mm_region axg_mem_map[] = {
  65        {
  66                .virt = 0x0UL,
  67                .phys = 0x0UL,
  68                .size = 0x80000000UL,
  69                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  70                         PTE_BLOCK_INNER_SHARE
  71        }, {
  72                .virt = 0xf0000000UL,
  73                .phys = 0xf0000000UL,
  74                .size = 0x10000000UL,
  75                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  76                         PTE_BLOCK_NON_SHARE |
  77                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
  78        }, {
  79                /* List terminator */
  80                0,
  81        }
  82};
  83
  84struct mm_region *mem_map = axg_mem_map;
  85
  86/* Configure the Ethernet MAC with the requested interface mode
  87 * with some optional flags.
  88 */
  89void meson_eth_init(phy_interface_t mode, unsigned int flags)
  90{
  91        switch (mode) {
  92        case PHY_INTERFACE_MODE_RGMII:
  93        case PHY_INTERFACE_MODE_RGMII_ID:
  94        case PHY_INTERFACE_MODE_RGMII_RXID:
  95        case PHY_INTERFACE_MODE_RGMII_TXID:
  96                /* Set RGMII mode */
  97                setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
  98                             AXG_ETH_REG_0_TX_PHASE(1) |
  99                             AXG_ETH_REG_0_TX_RATIO(4) |
 100                             AXG_ETH_REG_0_PHY_CLK_EN |
 101                             AXG_ETH_REG_0_CLK_EN);
 102                break;
 103
 104        case PHY_INTERFACE_MODE_RMII:
 105                /* Set RMII mode */
 106                out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
 107                                        AXG_ETH_REG_0_INVERT_RMII_CLK |
 108                                        AXG_ETH_REG_0_CLK_EN);
 109                break;
 110
 111        default:
 112                printf("Invalid Ethernet interface mode\n");
 113                return;
 114        }
 115
 116        /* Enable power gate */
 117        clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
 118}
 119