1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2013,2014 Renesas Electronics Corporation 4 * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5 */ 6 7#ifndef __EHCI_RMOBILE_H__ 8#define __EHCI_RMOBILE_H__ 9 10/* Register offset */ 11#define OHCI_OFFSET 0x00 12#define OHCI_SIZE 0x1000 13#define EHCI_OFFSET 0x1000 14#define EHCI_SIZE 0x1000 15 16#define EHCI_USBCMD (EHCI_OFFSET + 0x0020) 17 18/* USBCTR */ 19#define DIRPD (1 << 8) 20#define PLL_RST (1 << 2) 21#define PCICLK_MASK (1 << 1) 22#define USBH_RST (1 << 0) 23 24/* CMND_STS */ 25#define SERREN (1 << 8) 26#define PERREN (1 << 6) 27#define MASTEREN (1 << 2) 28#define MEMEN (1 << 1) 29 30/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ 31#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) 32 33/* AHBPCI_WIN1_CTR */ 34#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) 35#define AHB_CFG_AHBPCI 0x40000000 36#define AHB_CFG_HOST 0x80000000 37 38/* AHBPCI_WIN2_CTR */ 39#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) 40 41/* PCI_INT_ENABLE */ 42#define USBH_PMEEN (1 << 19) 43#define USBH_INTBEN (1 << 17) 44#define USBH_INTAEN (1 << 16) 45 46/* AHB_BUS_CTR */ 47#define SMODE_READY_CTR (1 << 17) 48#define SMODE_READ_BURST (1 << 16) 49#define MMODE_HBUSREQ (1 << 7) 50#define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) 51#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) 52#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) 53#define MMODE_WR_INCR (1 << 2) 54#define MMODE_BYTE_BURST (1 << 1) 55#define MMODE_HTRANS (1 << 0) 56 57/* PCI_ARBITER_CTR */ 58#define PCIBUS_PARK_TIMER 0x00FF0000 59#define PCIBUS_PARK_TIMER_SET 0x00070000 60#define PCIBP_MODE (1 << 12) 61#define PCIREQ7 (1 << 7) 62#define PCIREQ6 (1 << 6) 63#define PCIREQ5 (1 << 5) 64#define PCIREQ4 (1 << 4) 65#define PCIREQ3 (1 << 3) 66#define PCIREQ2 (1 << 2) 67#define PCIREQ1 (1 << 1) 68#define PCIREQ0 (1 << 0) 69 70#define SMSTPCR7 0xE615014C 71#define SMSTPCR703 (1 << 3) 72 73/* Init AHB master and slave functions of the host logic */ 74#define AHB_BUS_CTR_INIT \ 75 (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \ 76 MMODE_BYTE_BURST | MMODE_HTRANS) 77 78#define USBCTR_WIN_SIZE_1GB 0x800 79 80/* PCI Configuration Registers */ 81#define PCI_CONF_OHCI_OFFSET 0x10000 82#define PCI_CONF_EHCI_OFFSET 0x10100 83struct ahb_pciconf { 84 u32 vid_did; 85 u32 cmnd_sts; 86 u32 rev; 87 u32 cache_line; 88 u32 basead; 89}; 90 91/* PCI Configuration Registers for AHB-PCI Bridge Registers */ 92#define PCI_CONF_AHBPCI_OFFSET 0x10000 93struct ahbconf_pci_bridge { 94 u32 vid_did; /* 0x00 */ 95 u32 cmnd_sts; 96 u32 revid_cc; 97 u32 cls_lt_ht_bist; 98 u32 basead; /* 0x10 */ 99 u32 win1_basead; 100 u32 win2_basead; 101 u32 dummy0[5]; 102 u32 ssvdi_ssid; /* 0x2C */ 103 u32 dummy1[4]; 104 u32 intr_line_pin; 105}; 106 107/* AHB-PCI Bridge PCI Communication Registers */ 108#define AHBPCI_OFFSET 0x10800 109struct ahbcom_pci_bridge { 110 u32 pciahb_win1_ctr; /* 0x00 */ 111 u32 pciahb_win2_ctr; 112 u32 pciahb_dct_ctr; 113 u32 dummy0; 114 u32 ahbpci_win1_ctr; /* 0x10 */ 115 u32 ahbpci_win2_ctr; 116 u32 dummy1; 117 u32 ahbpci_dct_ctr; 118 u32 pci_int_enable; /* 0x20 */ 119 u32 pci_int_status; 120 u32 dummy2[2]; 121 u32 ahb_bus_ctr; /* 0x30 */ 122 u32 usbctr; 123 u32 dummy3[2]; 124 u32 pci_arbiter_ctr; /* 0x40 */ 125 u32 dummy4; 126 u32 pci_unit_rev; /* 0x48 */ 127}; 128 129struct rmobile_ehci_reg { 130 u32 hciversion; /* hciversion/caplength */ 131 u32 hcsparams; /* hcsparams */ 132 u32 hccparams; /* hccparams */ 133 u32 hcsp_portroute; /* hcsp_portroute */ 134 u32 usbcmd; /* usbcmd */ 135 u32 usbsts; /* usbsts */ 136 u32 usbintr; /* usbintr */ 137 u32 frindex; /* frindex */ 138 u32 ctrldssegment; /* ctrldssegment */ 139 u32 periodiclistbase; /* periodiclistbase */ 140 u32 asynclistaddr; /* asynclistaddr */ 141 u32 dummy[9]; 142 u32 configflag; /* configflag */ 143 u32 portsc; /* portsc */ 144}; 145 146#endif /* __EHCI_RMOBILE_H__ */ 147