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8
9#include <common.h>
10#include <pci.h>
11
12#if defined(CONFIG_OF_LIBFDT)
13#include <linux/libfdt.h>
14#include <fdt_support.h>
15#endif
16
17#include <asm/mpc8349_pci.h>
18
19#define MAX_BUSES 2
20
21DECLARE_GLOBAL_DATA_PTR;
22
23static struct pci_controller pci_hose[MAX_BUSES];
24static int pci_num_buses;
25
26static void pci_init_bus(int bus, struct pci_region *reg)
27{
28 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
29 volatile pot83xx_t *pot = immr->ios.pot;
30 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
31 struct pci_controller *hose = &pci_hose[bus];
32 u32 dev;
33 u16 reg16;
34 int i;
35
36 if (bus == 1)
37 pot += 3;
38
39
40 for (i = 0; i < 3; i++, reg++, pot++) {
41 if (reg->size == 0)
42 break;
43
44 hose->regions[i] = *reg;
45 hose->region_count++;
46
47 pot->potar = reg->bus_start >> 12;
48 pot->pobar = reg->phys_start >> 12;
49 pot->pocmr = ~(reg->size - 1) >> 12;
50
51 if (reg->flags & PCI_REGION_IO)
52 pot->pocmr |= POCMR_IO;
53#ifdef CONFIG_83XX_PCI_STREAMING
54 else if (reg->flags & PCI_REGION_PREFETCH)
55 pot->pocmr |= POCMR_SE;
56#endif
57
58 if (bus == 1)
59 pot->pocmr |= POCMR_DST;
60
61 pot->pocmr |= POCMR_EN;
62 }
63
64
65 pci_ctrl->pitar1 = 0;
66 pci_ctrl->pibar1 = 0;
67 pci_ctrl->piebar1 = 0;
68 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
69 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
70
71 i = hose->region_count++;
72 hose->regions[i].bus_start = 0;
73 hose->regions[i].phys_start = 0;
74 hose->regions[i].size = gd->ram_size;
75 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
76
77 hose->first_busno = pci_last_busno() + 1;
78 hose->last_busno = 0xff;
79
80 pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
81 CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
82
83 pci_register_hose(hose);
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87
88 reg16 = 0xff;
89 dev = PCI_BDF(hose->first_busno, 0, 0);
90 pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
91 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
92 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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94
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96
97 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
98 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
99 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
100
101#ifdef CONFIG_PCI_SCAN_SHOW
102 printf("PCI: Bus Dev VenId DevId Class Int\n");
103#endif
104#ifndef CONFIG_PCISLAVE
105
106
107
108 hose->last_busno = pci_hose_scan(hose);
109#endif
110}
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117
118
119void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
120{
121 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
122 int i;
123
124 if (num_buses > MAX_BUSES) {
125 printf("%d PCI buses requested, %d supported\n",
126 num_buses, MAX_BUSES);
127
128 num_buses = MAX_BUSES;
129 }
130
131 pci_num_buses = num_buses;
132
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136
137
138 udelay(100000);
139
140 for (i = 0; i < num_buses; i++)
141 immr->pci_ctrl[i].gcr = 1;
142
143
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145
146
147
148
149 udelay(1020000);
150
151 for (i = 0; i < num_buses; i++)
152 pci_init_bus(i, reg[i]);
153}
154
155#ifdef CONFIG_PCISLAVE
156
157#define PCI_FUNCTION_CONFIG 0x44
158#define PCI_FUNCTION_CFG_LOCK 0x20
159
160
161
162
163
164
165
166
167void mpc83xx_pcislave_unlock(int bus)
168{
169 struct pci_controller *hose = &pci_hose[bus];
170 u32 dev;
171 u16 reg16;
172
173
174 dev = PCI_BDF(hose->first_busno, 0, 0);
175 pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, ®16);
176 reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
177 pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
178
179
180 hose->last_busno = pci_hose_scan(hose);
181}
182#endif
183
184#if defined(CONFIG_OF_LIBFDT)
185void ft_pci_setup(void *blob, bd_t *bd)
186{
187 int nodeoffset;
188 int tmp[2];
189 const char *path;
190
191 if (pci_num_buses < 1)
192 return;
193
194 nodeoffset = fdt_path_offset(blob, "/aliases");
195 if (nodeoffset >= 0) {
196 path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
197 if (path) {
198 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
199 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
200 do_fixup_by_path(blob, path, "bus-range",
201 &tmp, sizeof(tmp), 1);
202
203 tmp[0] = cpu_to_be32(gd->pci_clk);
204 do_fixup_by_path(blob, path, "clock-frequency",
205 &tmp, sizeof(tmp[0]), 1);
206 }
207
208 if (pci_num_buses < 2)
209 return;
210
211 path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
212 if (path) {
213 tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
214 tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
215 do_fixup_by_path(blob, path, "bus-range",
216 &tmp, sizeof(tmp), 1);
217
218 tmp[0] = cpu_to_be32(gd->pci_clk);
219 do_fixup_by_path(blob, path, "clock-frequency",
220 &tmp, sizeof(tmp[0]), 1);
221 }
222 }
223}
224#endif
225