LXR uboot/arch/powerpc/cpu/mpc83xx/pcie.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2007-2009  Freescale Semiconductor, Inc.
   4 * Copyright (C) 2008-2009  MontaVista Software, Inc.
   5 *
   6 * Authors: Tony Li <tony.li@freescale.com>
   7 *          Anton Vorontsov <avorontsov@ru.mvista.com>
   8 */
   9
  10#include <common.h>
  11#include <pci.h>
  12#include <mpc83xx.h>
  13#include <asm/io.h>
  14
  15DECLARE_GLOBAL_DATA_PTR;
  16
  17#define PCIE_MAX_BUSES 2
  18
  19static struct {
  20        u32 base;
  21        u32 size;
  22} mpc83xx_pcie_cfg_space[] = {
  23        {
  24                .base = CONFIG_SYS_PCIE1_CFG_BASE,
  25                .size = CONFIG_SYS_PCIE1_CFG_SIZE,
  26        },
  27#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
  28        {
  29                .base = CONFIG_SYS_PCIE2_CFG_BASE,
  30                .size = CONFIG_SYS_PCIE2_CFG_SIZE,
  31        },
  32#endif
  33};
  34
  35#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
  36
  37/* private structure for mpc83xx pcie hose */
  38static struct mpc83xx_pcie_priv {
  39        u8 index;
  40} pcie_priv[PCIE_MAX_BUSES] = {
  41        {
  42                /* pcie controller 1 */
  43                .index = 0,
  44        },
  45        {
  46                /* pcie controller 2 */
  47                .index = 1,
  48        },
  49};
  50
  51static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
  52{
  53        int bus = PCI_BUS(dev) - hose->first_busno;
  54        immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  55        struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
  56        pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
  57        struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
  58        u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
  59        u32 dev_base = bus << 24 | devfn << 16;
  60
  61        if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
  62                return -1;
  63        /*
  64         * Workaround for the HW bug: for Type 0 configure transactions the
  65         * PCI-E controller does not check the device number bits and just
  66         * assumes that the device number bits are 0.
  67         */
  68        if (devfn & 0xf8)
  69                return -1;
  70
  71        out_le32(&out_win->tarl, dev_base);
  72        return 0;
  73}
  74
  75#define cfg_read(val, addr, type, op) \
  76        do { *val = op((type)(addr)); } while (0)
  77#define cfg_write(val, addr, type, op) \
  78        do { op((type *)(addr), (val)); } while (0)
  79
  80#define cfg_read_err(val) do { *val = -1; } while (0)
  81#define cfg_write_err(val) do { } while (0)
  82
  83#define PCIE_OP(rw, size, type, op)                                     \
  84static int pcie_##rw##_config_##size(struct pci_controller *hose,       \
  85                                     pci_dev_t dev, int offset,         \
  86                                     type val)                          \
  87{                                                                       \
  88        int ret;                                                        \
  89                                                                        \
  90        ret = mpc83xx_pcie_remap_cfg(hose, dev);                        \
  91        if (ret) {                                                      \
  92                cfg_##rw##_err(val);                                    \
  93                return ret;                                             \
  94        }                                                               \
  95        cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op);       \
  96        return 0;                                                       \
  97}
  98
  99PCIE_OP(read, byte, u8 *, in_8)
 100PCIE_OP(read, word, u16 *, in_le16)
 101PCIE_OP(read, dword, u32 *, in_le32)
 102PCIE_OP(write, byte, u8, out_8)
 103PCIE_OP(write, word, u16, out_le16)
 104PCIE_OP(write, dword, u32, out_le32)
 105
 106static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 107                                       u8 link)
 108{
 109        extern void disable_addr_trans(void); /* start.S */
 110        static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
 111        struct pci_controller *hose = &pcie_hose[bus];
 112        int i;
 113
 114        /*
 115         * There are no spare BATs to remap all PCI-E windows for U-Boot, so
 116         * disable translations. In general, this is not great solution, and
 117         * that's why we don't register PCI-E hoses by default.
 118         */
 119        disable_addr_trans();
 120
 121        for (i = 0; i < 2; i++, reg++) {
 122                if (reg->size == 0)
 123                        break;
 124
 125                hose->regions[i] = *reg;
 126                hose->region_count++;
 127        }
 128
 129        i = hose->region_count++;
 130        hose->regions[i].bus_start = 0;
 131        hose->regions[i].phys_start = 0;
 132        hose->regions[i].size = gd->ram_size;
 133        hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
 134
 135        i = hose->region_count++;
 136        hose->regions[i].bus_start = CONFIG_SYS_IMMR;
 137        hose->regions[i].phys_start = CONFIG_SYS_IMMR;
 138        hose->regions[i].size = 0x100000;
 139        hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
 140
 141        hose->first_busno = pci_last_busno() + 1;
 142        hose->last_busno = 0xff;
 143
 144        hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
 145
 146        hose->priv_data = &pcie_priv[bus];
 147
 148        pci_set_ops(hose,
 149                        pcie_read_config_byte,
 150                        pcie_read_config_word,
 151                        pcie_read_config_dword,
 152                        pcie_write_config_byte,
 153                        pcie_write_config_word,
 154                        pcie_write_config_dword);
 155
 156        if (!link)
 157                hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
 158
 159        pci_register_hose(hose);
 160
 161#ifdef CONFIG_PCI_SCAN_SHOW
 162        printf("PCI:   Bus Dev VenId DevId Class Int\n");
 163#endif
 164        /*
 165         * Hose scan.
 166         */
 167        hose->last_busno = pci_hose_scan(hose);
 168}
 169
 170#else
 171
 172static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 173                                       u8 link) {}
 174
 175#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
 176
 177int get_pcie_clk(int index)
 178{
 179        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 180        u32 pci_sync_in;
 181        u8 spmf;
 182        u8 clkin_div;
 183        u32 sccr;
 184        u32 csb_clk;
 185        u32 testval;
 186
 187        clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
 188        sccr = im->clk.sccr;
 189        pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
 190        spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
 191        csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
 192
 193        if (index)
 194                testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT;
 195        else
 196                testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT;
 197
 198        switch (testval) {
 199        case 0:
 200                return 0;
 201        case 1:
 202                return csb_clk;
 203        case 2:
 204                return csb_clk / 2;
 205        case 3:
 206                return csb_clk / 3;
 207        }
 208
 209        return 0;
 210}
 211
 212static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
 213{
 214        immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 215        pex83xx_t *pex = &immr->pciexp[bus];
 216        struct pex_outbound_window *out_win;
 217        struct pex_inbound_window *in_win;
 218        void *hose_cfg_base;
 219        unsigned int ram_sz;
 220        unsigned int barl;
 221        unsigned int tar;
 222        u16 reg16;
 223        int i;
 224
 225        /* Enable pex csb bridge inbound & outbound transactions */
 226        out_le32(&pex->bridge.pex_csb_ctrl,
 227                in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
 228                PEX_CSB_CTRL_IBPIOE);
 229
 230        /* Enable bridge outbound */
 231        out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
 232                PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
 233                PEX_CSB_OBCTRL_CFGWE);
 234
 235        out_win = &pex->bridge.pex_outbound_win[0];
 236        out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
 237                        mpc83xx_pcie_cfg_space[bus].size);
 238        out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
 239        out_le32(&out_win->tarl, 0);
 240        out_le32(&out_win->tarh, 0);
 241
 242        for (i = 0; i < 2; i++) {
 243                u32 ar;
 244
 245                if (reg[i].size == 0)
 246                        break;
 247
 248                out_win = &pex->bridge.pex_outbound_win[i + 1];
 249                out_le32(&out_win->bar, reg[i].phys_start);
 250                out_le32(&out_win->tarl, reg[i].bus_start);
 251                out_le32(&out_win->tarh, 0);
 252                ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
 253                if (reg[i].flags & PCI_REGION_IO)
 254                        ar |= PEX_OWAR_TYPE_IO;
 255                else
 256                        ar |= PEX_OWAR_TYPE_MEM;
 257                out_le32(&out_win->ar, ar);
 258        }
 259
 260        out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
 261
 262        ram_sz = gd->ram_size;
 263        barl = 0;
 264        tar = 0;
 265        i = 0;
 266        while (ram_sz > 0) {
 267                in_win = &pex->bridge.pex_inbound_win[i];
 268                out_le32(&in_win->barl, barl);
 269                out_le32(&in_win->barh, 0x0);
 270                out_le32(&in_win->tar, tar);
 271                if (ram_sz >= 0x10000000) {
 272                        /* The maxium windows size is 256M */
 273                        out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
 274                                PEX_IWAR_TYPE_PF | 0x0FFFF000);
 275                        barl += 0x10000000;
 276                        tar += 0x10000000;
 277                        ram_sz -= 0x10000000;
 278                } else {
 279                        /* The UM  is not clear here.
 280                         * So, round up to even Mb boundary */
 281
 282                        ram_sz = ram_sz >> (20 +
 283                                        ((ram_sz & 0xFFFFF) ? 1 : 0));
 284                        if (!(ram_sz % 2))
 285                                ram_sz -= 1;
 286                        out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
 287                                PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
 288                        ram_sz = 0;
 289                }
 290                i++;
 291        }
 292
 293        in_win = &pex->bridge.pex_inbound_win[i];
 294        out_le32(&in_win->barl, CONFIG_SYS_IMMR);
 295        out_le32(&in_win->barh, 0);
 296        out_le32(&in_win->tar, CONFIG_SYS_IMMR);
 297        out_le32(&in_win->ar, PEX_IWAR_EN |
 298                PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
 299
 300        /* Enable the host virtual INTX interrupts */
 301        out_le32(&pex->bridge.pex_int_axi_misc_enb,
 302                in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
 303
 304        /* Hose configure header is memory-mapped */
 305        hose_cfg_base = (void *)pex;
 306
 307        /* Configure the PCIE controller core clock ratio */
 308        out_le32(hose_cfg_base + PEX_GCLK_RATIO,
 309                ((get_pcie_clk(bus) / 1000000) * 16) / 333);
 310        udelay(1000000);
 311
 312        /* Do Type 1 bridge configuration */
 313        out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
 314        out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
 315        out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
 316
 317        /*
 318         * Write to Command register
 319         */
 320        reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
 321        reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
 322                        PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
 323        out_le16(hose_cfg_base + PCI_COMMAND, reg16);
 324
 325        /*
 326         * Clear non-reserved bits in status register.
 327         */
 328        out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
 329        out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
 330        out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
 331
 332        printf("PCIE%d: ", bus);
 333
 334#define PCI_LTSSM       0x404 /* PCIe Link Training, Status State Machine */
 335#define PCI_LTSSM_L0    0x16 /* L0 state */
 336        reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
 337        if (reg16 >= PCI_LTSSM_L0)
 338                printf("link\n");
 339        else
 340                printf("No link\n");
 341
 342        mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
 343}
 344
 345/*
 346 * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
 347 * must have been set to cover all of the requested regions.
 348 */
 349void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
 350{
 351        int i;
 352
 353        /*
 354         * Release PCI RST Output signal.
 355         * Power on to RST high must be at least 100 ms as per PCI spec.
 356         * On warm boots only 1 ms is required, but we play it safe.
 357         */
 358        udelay(100000);
 359
 360        if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
 361                printf("Second PCIE host contoller not configured!\n");
 362                num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
 363        }
 364
 365        for (i = 0; i < num_buses; i++)
 366                mpc83xx_pcie_init_bus(i, reg[i]);
 367}
 368