1
2
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5
6#include <common.h>
7#include <env.h>
8#include <time.h>
9#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
10#include <hwconfig.h>
11#endif
12#include <asm/fsl_serdes.h>
13#include <asm/immap_85xx.h>
14#include <asm/io.h>
15#include <asm/processor.h>
16#include <asm/fsl_law.h>
17#include <linux/errno.h>
18#include "fsl_corenet_serdes.h"
19
20
21
22
23
24
25
26#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
27#ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
28#error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
29#endif
30#endif
31
32static u32 serdes_prtcl_map;
33
34#ifdef DEBUG
35static const char *serdes_prtcl_str[] = {
36 [NONE] = "NA",
37 [PCIE1] = "PCIE1",
38 [PCIE2] = "PCIE2",
39 [PCIE3] = "PCIE3",
40 [PCIE4] = "PCIE4",
41 [SATA1] = "SATA1",
42 [SATA2] = "SATA2",
43 [SRIO1] = "SRIO1",
44 [SRIO2] = "SRIO2",
45 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
46 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
47 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
48 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
49 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
50 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
51 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
52 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
53 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
54 [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
55 [XAUI_FM1] = "XAUI_FM1",
56 [XAUI_FM2] = "XAUI_FM2",
57 [AURORA] = "DEBUG",
58};
59#endif
60
61static const struct {
62 int idx;
63 unsigned int lpd;
64 int bank;
65} lanes[SRDS_MAX_LANES] = {
66 { 0, 152, FSL_SRDS_BANK_1 },
67 { 1, 153, FSL_SRDS_BANK_1 },
68 { 2, 154, FSL_SRDS_BANK_1 },
69 { 3, 155, FSL_SRDS_BANK_1 },
70 { 4, 156, FSL_SRDS_BANK_1 },
71 { 5, 157, FSL_SRDS_BANK_1 },
72 { 6, 158, FSL_SRDS_BANK_1 },
73 { 7, 159, FSL_SRDS_BANK_1 },
74 { 8, 160, FSL_SRDS_BANK_1 },
75 { 9, 161, FSL_SRDS_BANK_1 },
76 { 16, 162, FSL_SRDS_BANK_2 },
77 { 17, 163, FSL_SRDS_BANK_2 },
78 { 18, 164, FSL_SRDS_BANK_2 },
79 { 19, 165, FSL_SRDS_BANK_2 },
80#ifdef CONFIG_ARCH_P4080
81 { 20, 170, FSL_SRDS_BANK_3 },
82 { 21, 171, FSL_SRDS_BANK_3 },
83 { 22, 172, FSL_SRDS_BANK_3 },
84 { 23, 173, FSL_SRDS_BANK_3 },
85#else
86 { 20, 166, FSL_SRDS_BANK_3 },
87 { 21, 167, FSL_SRDS_BANK_3 },
88 { 22, 168, FSL_SRDS_BANK_3 },
89 { 23, 169, FSL_SRDS_BANK_3 },
90#endif
91#if SRDS_MAX_BANK > 3
92 { 24, 175, FSL_SRDS_BANK_4 },
93 { 25, 176, FSL_SRDS_BANK_4 },
94#endif
95};
96
97int serdes_get_lane_idx(int lane)
98{
99 return lanes[lane].idx;
100}
101
102int serdes_get_bank_by_lane(int lane)
103{
104 return lanes[lane].bank;
105}
106
107int serdes_lane_enabled(int lane)
108{
109 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
110 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
111
112 int bank = lanes[lane].bank;
113 int word = lanes[lane].lpd / 32;
114 int bit = lanes[lane].lpd % 32;
115
116 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
117 return 0;
118
119#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
120
121
122
123
124
125 if (bank > 0)
126 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
127#endif
128
129 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
130}
131
132int is_serdes_configured(enum srds_prtcl device)
133{
134 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
135
136
137 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
138 return 0;
139
140 if (!(serdes_prtcl_map & (1 << NONE)))
141 fsl_serdes_init();
142
143 return (1 << device) & serdes_prtcl_map;
144}
145
146static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
147{
148 int i;
149
150 for (i = 0; i < SRDS_MAX_LANES; i++) {
151 if (serdes_get_prtcl(prtcl, i) == device)
152 return i;
153 }
154
155 return -ENODEV;
156}
157
158
159
160
161
162
163
164
165int serdes_get_first_lane(enum srds_prtcl device)
166{
167 u32 prtcl;
168 const ccsr_gur_t *gur;
169
170 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
171
172
173 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
174 return -ENODEV;
175
176 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
177
178 return __serdes_get_first_lane(prtcl, device);
179}
180
181#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
182
183
184
185
186
187
188
189static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device)
190{
191 int lane;
192
193 lane = __serdes_get_first_lane(prtcl, device);
194 if (unlikely(lane < 0))
195 return lane;
196
197 return serdes_get_bank_by_lane(lane);
198}
199
200static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device,
201 int first)
202{
203 int lane;
204
205 for (lane = first; lane < SRDS_MAX_LANES; lane++) {
206 if (serdes_get_prtcl(prtcl, lane) != device)
207 break;
208 }
209
210 return lane - first;
211}
212
213static void __serdes_reset_rx(serdes_corenet_t *regs,
214 uint32_t prtcl,
215 enum srds_prtcl device)
216{
217 int lane, idx, first, last;
218
219 lane = __serdes_get_first_lane(prtcl, device);
220 if (unlikely(lane < 0))
221 return;
222 first = serdes_get_lane_idx(lane);
223 last = first + __serdes_get_lane_count(prtcl, device, lane);
224
225
226
227
228
229 for (idx = first; idx < last; idx++)
230 clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
231
232
233 udelay(1);
234
235
236
237
238
239 for (idx = first; idx < last; idx++)
240 setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
241}
242
243void serdes_reset_rx(enum srds_prtcl device)
244{
245 u32 prtcl;
246 const ccsr_gur_t *gur;
247 serdes_corenet_t *regs;
248
249 if (unlikely(device == NONE))
250 return;
251
252 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
253
254
255 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
256 return;
257
258 regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
259 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
260
261 __serdes_reset_rx(regs, prtcl, device);
262}
263#endif
264
265#ifndef CONFIG_SYS_DCSRBAR_PHYS
266#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000
267#define CONFIG_SYS_DCSRBAR 0x80000000
268#define __DCSR_NOT_DEFINED_BY_CONFIG
269#endif
270
271#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
272
273
274
275
276
277
278
279
280
281
282
283static void enable_bank(ccsr_gur_t *gur, int bank)
284{
285 u32 rcw5;
286 u32 temp_lpd_b = srds_lpd_b[bank];
287
288
289
290
291
292 if (temp_lpd_b == 0xF)
293 temp_lpd_b = 0xE;
294
295
296
297
298
299 rcw5 = in_be32(gur->rcwsr + 5);
300 if (bank == FSL_SRDS_BANK_2) {
301 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
302 rcw5 |= temp_lpd_b << 26;
303 } else if (bank == FSL_SRDS_BANK_3) {
304 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
305 rcw5 |= temp_lpd_b << 18;
306 } else {
307 printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
308 return;
309 }
310
311
312
313
314 {
315#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
316 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
317 int law_index;
318 if (law.index == -1)
319 law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
320 LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
321 else
322 set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
323 LAW_TRGT_IF_DCSR);
324#endif
325 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
326 out_be32(p, rcw5);
327#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
328 if (law.index == -1)
329 disable_law(law_index);
330 else
331 set_law(law.index, law.addr, law.size, law.trgt_id);
332#endif
333 }
334}
335
336
337
338
339
340
341
342
343
344static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
345 u32 devdisr, u32 devdisr2, int cfg)
346{
347 int srds_ratio_b2;
348 int rfck_sel;
349
350
351
352
353
354
355
356
357
358 clrbits_be32(&gur->devdisr, devdisr);
359 clrbits_be32(&gur->devdisr2, devdisr2);
360
361
362
363
364
365
366
367 switch (cfg) {
368 case 0x19:
369
370
371
372
373 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
374 SRDS_PLLCR1_PLL_BWSEL);
375 break;
376
377 case 0x0f:
378 case 0x10:
379
380
381
382
383
384
385
386 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
387
388
389 switch (srds_ratio_b2) {
390 case 1:
391 rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
392 break;
393 case 2:
394 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
395 break;
396 default:
397 printf("SERDES: bad SRDS_RATIO_B2 %d\n",
398 srds_ratio_b2);
399 return;
400 }
401
402 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
403 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
404
405 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
406 SRDS_PLLCR0_FRATE_SEL_MASK,
407 SRDS_PLLCR0_FRATE_SEL_6_25);
408 break;
409 }
410
411 enable_bank(gur, FSL_SRDS_BANK_3);
412}
413#endif
414
415#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
416
417
418
419
420static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
421{
422 enum srds_prtcl device;
423
424 switch (cfg) {
425 case 0x13:
426 case 0x16:
427
428
429
430
431 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
432 SRDS_PLLCR1_PLL_BWSEL);
433 break;
434 case 0x19:
435
436
437
438
439 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
440 SRDS_PLLCR1_PLL_BWSEL);
441 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
442 SRDS_PLLCR1_PLL_BWSEL);
443 break;
444 }
445
446
447
448
449
450 for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
451 if (is_serdes_configured(device)) {
452 int bank = serdes_get_bank_by_device(cfg, device);
453
454 clrbits_be32(®s->bank[bank].pllcr1,
455 SRDS_PLLCR1_PLL_BWSEL);
456 }
457 }
458}
459#endif
460
461
462
463
464static void wait_for_rstdone(unsigned int bank)
465{
466 serdes_corenet_t *srds_regs =
467 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
468 unsigned long long end_tick;
469 u32 rstctl;
470
471
472 end_tick = usec2ticks(1000000) + get_ticks();
473 do {
474 rstctl = in_be32(&srds_regs->bank[bank].rstctl);
475 if (rstctl & SRDS_RSTCTL_RSTDONE)
476 break;
477 } while (end_tick > get_ticks());
478
479 if (!(rstctl & SRDS_RSTCTL_RSTDONE))
480 printf("SERDES: timeout resetting bank %u\n", bank + 1);
481}
482
483
484static void __soc_serdes_init(void)
485{
486
487};
488void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
489
490void fsl_serdes_init(void)
491{
492 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
493 int cfg;
494 serdes_corenet_t *srds_regs;
495#ifdef CONFIG_ARCH_P5040
496 serdes_corenet_t *srds2_regs;
497#endif
498 int lane, bank, idx;
499 int have_bank[SRDS_MAX_BANK] = {};
500#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
501 u32 serdes8_devdisr = 0;
502 u32 serdes8_devdisr2 = 0;
503 char srds_lpd_opt[16];
504 const char *srds_lpd_arg;
505 size_t arglen;
506#endif
507#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
508 int need_serdes_a001;
509#endif
510#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
511 char buffer[HWCONFIG_BUFFER_SIZE];
512 char *buf = NULL;
513
514
515
516
517
518 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
519 buf = buffer;
520#endif
521 if (serdes_prtcl_map & (1 << NONE))
522 return;
523
524
525 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
526 return;
527
528 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
529 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
530 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
531
532 if (!is_serdes_prtcl_valid(cfg)) {
533 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
534 return;
535 }
536
537#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
538
539
540
541
542
543#define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
544 if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) {
545 printf("Warning: SERDES8 requires banks two and "
546 "three to be disabled in the RCW\n");
547 }
548
549
550
551
552
553
554 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
555 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
556 srds_lpd_arg =
557 hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
558 if (srds_lpd_arg)
559 srds_lpd_b[bank] =
560 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
561 }
562
563 if ((cfg == 0xf) || (cfg == 0x10)) {
564
565
566
567
568 srds_lpd_b[FSL_SRDS_BANK_3] = 0xF;
569 }
570#endif
571
572
573 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
574 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
575 if (serdes_lane_enabled(lane)) {
576 have_bank[serdes_get_bank_by_lane(lane)] = 1;
577 serdes_prtcl_map |= (1 << lane_prtcl);
578 }
579 }
580
581#ifdef CONFIG_ARCH_P5040
582
583
584
585
586
587
588
589
590 switch (cfg) {
591 case 0x0:
592 case 0x1:
593 case 0x2:
594 case 0x3:
595 case 0x4:
596 case 0x5:
597 case 0x6:
598 case 0x7:
599 serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
600 break;
601 default:
602 srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
603
604
605 setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
606 }
607#endif
608
609 soc_serdes_init();
610
611
612 serdes_prtcl_map |= (1 << NONE);
613
614#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
615
616
617
618
619 if (have_bank[FSL_SRDS_BANK_2])
620 have_bank[FSL_SRDS_BANK_3] = 1;
621#endif
622
623#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
624
625
626
627
628
629
630
631 need_serdes_a001 =
632 !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3];
633#endif
634
635
636 for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
637 if (!have_bank[bank]) {
638 printf("SERDES: bank %d disabled\n", bank + 1);
639#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
640
641
642
643
644
645 if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2))
646 setbits_be32(&srds_regs->bank[bank].rstctl,
647 SRDS_RSTCTL_SDPD);
648#else
649 setbits_be32(&srds_regs->bank[bank].rstctl,
650 SRDS_RSTCTL_SDPD);
651#endif
652 }
653 }
654
655#ifdef CONFIG_SYS_FSL_ERRATUM_A004699
656
657
658
659
660
661
662
663
664
665
666 for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
667
668 unsigned int lane;
669
670 for (lane = 0; lane < SRDS_MAX_LANES; lane++)
671 if (lanes[lane].bank == bank)
672 break;
673 idx = lanes[lane].idx;
674
675
676
677
678
679 if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
680
681 setbits_be32(&srds_regs->bank[bank].pllcr0,
682 SRDS_PLLCR0_PVCOCNT_EN);
683 }
684 }
685#endif
686
687#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
688 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
689 enum srds_prtcl lane_prtcl;
690
691 idx = serdes_get_lane_idx(lane);
692 lane_prtcl = serdes_get_prtcl(cfg, lane);
693
694#ifdef DEBUG
695 switch (lane) {
696 case 0:
697 puts("Bank1: ");
698 break;
699 case 10:
700 puts("\nBank2: ");
701 break;
702 case 14:
703 puts("\nBank3: ");
704 break;
705 default:
706 break;
707 }
708
709 printf("%s ", serdes_prtcl_str[lane_prtcl]);
710#endif
711
712#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
713
714
715
716
717
718
719
720
721
722 switch (lane_prtcl) {
723 case SGMII_FM1_DTSEC1:
724 case SGMII_FM1_DTSEC2:
725 case SGMII_FM1_DTSEC3:
726 case SGMII_FM1_DTSEC4:
727 case SGMII_FM2_DTSEC1:
728 case SGMII_FM2_DTSEC2:
729 case SGMII_FM2_DTSEC3:
730 case SGMII_FM2_DTSEC4:
731 case SGMII_FM2_DTSEC5:
732 case XAUI_FM1:
733 case XAUI_FM2:
734 case SRIO1:
735 case SRIO2:
736 case AURORA:
737 out_be32(&srds_regs->lane[idx].ttlcr0,
738 SRDS_TTLCR0_FLT_SEL_KFR_26 |
739 SRDS_TTLCR0_FLT_SEL_KPH_28 |
740 SRDS_TTLCR0_FLT_SEL_750PPM |
741 SRDS_TTLCR0_FREQOVD_EN);
742 break;
743 default:
744 break;
745 }
746#endif
747
748#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
749 switch (lane_prtcl) {
750 case PCIE1:
751 case PCIE2:
752 case PCIE3:
753 serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
754 (lane_prtcl - PCIE1);
755 break;
756 case SRIO1:
757 case SRIO2:
758 serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
759 (lane_prtcl - SRIO1);
760 break;
761 case SGMII_FM1_DTSEC1:
762 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
763 FSL_CORENET_DEVDISR2_DTSEC1_1;
764 break;
765 case SGMII_FM1_DTSEC2:
766 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
767 FSL_CORENET_DEVDISR2_DTSEC1_2;
768 break;
769 case SGMII_FM1_DTSEC3:
770 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
771 FSL_CORENET_DEVDISR2_DTSEC1_3;
772 break;
773 case SGMII_FM1_DTSEC4:
774 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
775 FSL_CORENET_DEVDISR2_DTSEC1_4;
776 break;
777 case SGMII_FM2_DTSEC1:
778 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
779 FSL_CORENET_DEVDISR2_DTSEC2_1;
780 break;
781 case SGMII_FM2_DTSEC2:
782 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
783 FSL_CORENET_DEVDISR2_DTSEC2_2;
784 break;
785 case SGMII_FM2_DTSEC3:
786 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
787 FSL_CORENET_DEVDISR2_DTSEC2_3;
788 break;
789 case SGMII_FM2_DTSEC4:
790 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
791 FSL_CORENET_DEVDISR2_DTSEC2_4;
792 break;
793 case SGMII_FM2_DTSEC5:
794 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
795 FSL_CORENET_DEVDISR2_DTSEC2_5;
796 break;
797 case XAUI_FM1:
798 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
799 FSL_CORENET_DEVDISR2_10GEC1;
800 break;
801 case XAUI_FM2:
802 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
803 FSL_CORENET_DEVDISR2_10GEC2;
804 break;
805 case AURORA:
806 break;
807 default:
808 break;
809 }
810
811#endif
812 }
813#endif
814
815#ifdef DEBUG
816 puts("\n");
817#endif
818
819#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
820 p4080_erratum_serdes_a005(srds_regs, cfg);
821#endif
822
823 for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
824 bank = idx;
825
826#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
827
828
829
830
831
832
833 if (idx == 1)
834 bank = FSL_SRDS_BANK_3;
835 else if (idx == 2)
836 bank = FSL_SRDS_BANK_2;
837#endif
838
839
840 if (!have_bank[bank])
841 continue;
842
843#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
844 if (idx == 1) {
845
846
847
848
849
850
851 p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
852 serdes8_devdisr2, cfg);
853 } else if (idx == 2) {
854
855 enable_bank(gur, FSL_SRDS_BANK_2);
856 }
857#endif
858
859 wait_for_rstdone(bank);
860 }
861
862#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
863 if (need_serdes_a001) {
864
865 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl,
866 SRDS_RSTCTL_SDPD);
867 }
868#endif
869}
870
871const char *serdes_clock_to_string(u32 clock)
872{
873 switch (clock) {
874 case SRDS_PLLCR0_RFCK_SEL_100:
875 return "100";
876 case SRDS_PLLCR0_RFCK_SEL_125:
877 return "125";
878 case SRDS_PLLCR0_RFCK_SEL_156_25:
879 return "156.25";
880 case SRDS_PLLCR0_RFCK_SEL_161_13:
881 return "161.1328123";
882 default:
883 return "150";
884 }
885}
886
887