LXR uboot/board/Marvell/db-88f6820-amc/db-88f6820-amc.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
   4 */
   5
   6#include <common.h>
   7#include <i2c.h>
   8#include <miiphy.h>
   9#include <netdev.h>
  10#include <asm/io.h>
  11#include <asm/arch/cpu.h>
  12#include <asm/arch/soc.h>
  13
  14#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  15#include <../serdes/a38x/high_speed_env_spec.h>
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19/*
  20 * Those values and defines are taken from the Marvell U-Boot version
  21 * "u-boot-2013.01-2016_T1.0.eng_drop_v10"
  22 */
  23#define DB_AMC_88F68XX_GPP_OUT_ENA_LOW                                  \
  24        (~(BIT(29)))
  25#define DB_AMC_88F68XX_GPP_OUT_ENA_MID                                  \
  26        (~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21)))
  27#define DB_AMC_88F68XX_GPP_OUT_VAL_LOW  (BIT(29))
  28#define DB_AMC_88F68XX_GPP_OUT_VAL_MID  0x0
  29#define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH 0x0
  30#define DB_AMC_88F68XX_GPP_POL_LOW      0x0
  31#define DB_AMC_88F68XX_GPP_POL_MID      0x0
  32
  33static struct serdes_map board_serdes_map[] = {
  34        {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  35        {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  36        {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  37        {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  38        {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  39        {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  40};
  41
  42int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  43{
  44        *serdes_map_array = board_serdes_map;
  45        *count = ARRAY_SIZE(board_serdes_map);
  46        return 0;
  47}
  48
  49/*
  50 * Define the DDR layout / topology here in the board file. This will
  51 * be used by the DDR3 init code in the SPL U-Boot version to configure
  52 * the DDR3 controller.
  53 */
  54static struct mv_ddr_topology_map board_topology_map = {
  55        DEBUG_LEVEL_ERROR,
  56        0x1, /* active interfaces */
  57        /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  58        { { { {0x1, 0, 0, 0},
  59              {0x1, 0, 0, 0},
  60              {0x1, 0, 0, 0},
  61              {0x1, 0, 0, 0},
  62              {0x1, 0, 0, 0} },
  63            SPEED_BIN_DDR_1866L,        /* speed_bin */
  64            MV_DDR_DEV_WIDTH_8BIT,      /* memory_width */
  65            MV_DDR_DIE_CAP_2GBIT,       /* mem_size */
  66            MV_DDR_FREQ_800,            /* frequency */
  67            0, 0,                       /* cas_wl cas_l */
  68            MV_DDR_TEMP_LOW,            /* temperature */
  69            MV_DDR_TIM_DEFAULT} },      /* timing */
  70        BUS_MASK_32BIT,                 /* Busses mask */
  71        MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
  72        { {0} },                        /* raw spd data */
  73        {0}                             /* timing parameters */
  74};
  75
  76struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  77{
  78        /* Return the board topology as defined in the board code */
  79        return &board_topology_map;
  80}
  81
  82int board_early_init_f(void)
  83{
  84        /* Configure MPP */
  85        writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  86        writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  87        writel(0x55066011, MVEBU_MPP_BASE + 0x08);
  88        writel(0x05055550, MVEBU_MPP_BASE + 0x0c);
  89        writel(0x05055555, MVEBU_MPP_BASE + 0x10);
  90        writel(0x01106565, MVEBU_MPP_BASE + 0x14);
  91        writel(0x40000000, MVEBU_MPP_BASE + 0x18);
  92        writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
  93
  94        /* Set GPP Out value */
  95        writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  96        writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  97
  98        /* Set GPP Polarity */
  99        writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
 100        writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
 101
 102        /* Set GPP Out Enable */
 103        writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
 104        writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
 105
 106        return 0;
 107}
 108
 109int board_init(void)
 110{
 111        /* adress of boot parameters */
 112        gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 113
 114        return 0;
 115}
 116
 117int checkboard(void)
 118{
 119        puts("Board: Marvell DB-88F6820-AMC\n");
 120
 121        return 0;
 122}
 123
 124int board_eth_init(bd_t *bis)
 125{
 126        cpu_eth_init(bis); /* Built in controller(s) come first */
 127        return pci_eth_init(bis);
 128}
 129