LXR uboot/board/Synology/ds109/ds109.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2009-2012
   4 * Wojciech Dubowik <wojciech.dubowik@neratec.com>
   5 * Luka Perkov <luka@openwrt.org>
   6 */
   7
   8#include <common.h>
   9#include <miiphy.h>
  10#include <asm/setup.h>
  11#include <asm/arch/cpu.h>
  12#include <asm/arch/soc.h>
  13#include <asm/arch/mpp.h>
  14#include "ds109.h"
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18int board_early_init_f(void)
  19{
  20        /*
  21         * default gpio configuration
  22         * There are maximum 64 gpios controlled through 2 sets of registers
  23         * the below configuration configures mainly initial LED status
  24         */
  25        mvebu_config_gpio(DS109_OE_VAL_LOW,
  26                          DS109_OE_VAL_HIGH,
  27                          DS109_OE_LOW, DS109_OE_HIGH);
  28
  29        /* Multi-Purpose Pins Functionality configuration */
  30        static const u32 kwmpp_config[] = {
  31                MPP0_SPI_SCn,           /* SPI Flash */
  32                MPP1_SPI_MOSI,
  33                MPP2_SPI_SCK,
  34                MPP3_SPI_MISO,
  35                MPP4_GPIO,
  36                MPP5_GPO,
  37                MPP6_SYSRST_OUTn,       /* Reset signal */
  38                MPP7_GPO,
  39                MPP8_TW_SDA,            /* I2C */
  40                MPP9_TW_SCK,            /* I2C */
  41                MPP10_UART0_TXD,
  42                MPP11_UART0_RXD,
  43                MPP12_GPO,
  44                MPP13_UART1_TXD,
  45                MPP14_UART1_RXD,
  46                MPP15_GPIO,
  47                MPP16_GPIO,
  48                MPP17_GPIO,
  49                MPP18_GPO,
  50                MPP19_GPO,
  51                MPP20_SATA1_ACTn,
  52                MPP21_SATA0_ACTn,
  53                MPP22_GPIO,             /* HDD2 FAIL LED */
  54                MPP23_GPIO,             /* HDD1 FAIL LED */
  55                MPP24_GPIO,
  56                MPP25_GPIO,
  57                MPP26_GPIO,
  58                MPP27_GPIO,
  59                MPP28_GPIO,
  60                MPP29_GPIO,
  61                MPP30_GPIO,
  62                MPP31_GPIO,             /* HDD2 */
  63                MPP32_GPIO,             /* FAN A */
  64                MPP33_GPIO,             /* FAN B */
  65                MPP34_GPIO,             /* FAN C */
  66                MPP35_GPIO,             /* FAN SENSE */
  67                MPP36_GPIO,
  68                MPP37_GPIO,
  69                MPP38_GPIO,
  70                MPP39_GPIO,
  71                MPP40_GPIO,
  72                MPP41_GPIO,
  73                MPP42_GPIO,
  74                MPP43_GPIO,
  75                MPP44_GPIO,
  76                MPP45_GPIO,
  77                MPP46_GPIO,
  78                MPP47_GPIO,
  79                MPP48_GPIO,
  80                MPP49_GPIO,
  81                0
  82        };
  83        kirkwood_mpp_conf(kwmpp_config, NULL);
  84        return 0;
  85}
  86
  87int board_init(void)
  88{
  89        /* address of boot parameters */
  90        gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  91
  92        return 0;
  93}
  94
  95/* Synology reset uses UART */
  96#include <ns16550.h>
  97#define SOFTWARE_SHUTDOWN   0x31
  98#define SOFTWARE_REBOOT     0x43
  99#define CONFIG_SYS_NS16550_COM2         KW_UART1_BASE
 100void reset_misc(void)
 101{
 102        int b_d;
 103        printf("Synology reset...");
 104        udelay(50000);
 105
 106        b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
 107                CONFIG_SYS_NS16550_CLK, 9600);
 108        NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
 109        NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
 110}
 111
 112/* Support old kernels */
 113void setup_board_tags(struct tag **in_params)
 114{
 115        unsigned int boardId;
 116        struct tag *params;
 117        struct tag_mv_uboot *t;
 118        int i;
 119
 120        printf("Synology board tags...");
 121        params = *in_params;
 122        t = (struct tag_mv_uboot *)&params->u;
 123
 124        t->uboot_version = VER_NUM;
 125
 126        boardId = SYNO_DS109_ID;
 127        t->uboot_version |= boardId;
 128
 129        t->tclk = CONFIG_SYS_TCLK;
 130        t->sysclk = CONFIG_SYS_TCLK*2;
 131
 132        t->isusbhost = 1;
 133        for (i = 0; i < 4; i++) {
 134                memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
 135                t->mtu[i] = 0;
 136        }
 137
 138        params->hdr.tag = ATAG_MV_UBOOT;
 139        params->hdr.size = tag_size(tag_mv_uboot);
 140        params = tag_next(params);
 141        *in_params = params;
 142}
 143
 144#ifdef CONFIG_RESET_PHY_R
 145/* Configure and enable MV88E1116 PHY */
 146void reset_phy(void)
 147{
 148        u16 reg;
 149        u16 devadr;
 150        char *name = "egiga0";
 151
 152        if (miiphy_set_current_dev(name))
 153                return;
 154
 155        /* command to read PHY dev address */
 156        if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
 157                printf("Error: 88E1116 could not read PHY dev address\n");
 158                return;
 159        }
 160
 161        /*
 162         * Enable RGMII delay on Tx and Rx for CPU port
 163         * Ref: sec 4.7.2 of chip datasheet
 164         */
 165        miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 166        miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
 167        reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 168        miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
 169        miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 170
 171        /* reset the phy */
 172        miiphy_reset(name, devadr);
 173
 174        printf("88E1116 Initialized on %s\n", name);
 175}
 176#endif /* CONFIG_RESET_PHY_R */
 177