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6
7#include <common.h>
8#include <dm.h>
9#include <malloc.h>
10#include <errno.h>
11#include <netdev.h>
12#include <asm/io.h>
13#include <linux/compiler.h>
14#include <dm/platform_data/serial_pl01x.h>
15#include "pcie.h"
16#include <asm/armv8/mmu.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20static const struct pl01x_serial_platdata serial_platdata = {
21 .base = V2M_UART0,
22 .type = TYPE_PL011,
23 .clock = CONFIG_PL011_CLOCK,
24};
25
26U_BOOT_DEVICE(vexpress_serials) = {
27 .name = "serial_pl01x",
28 .platdata = &serial_platdata,
29};
30
31static struct mm_region vexpress64_mem_map[] = {
32 {
33 .virt = 0x0UL,
34 .phys = 0x0UL,
35 .size = 0x80000000UL,
36 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
37 PTE_BLOCK_NON_SHARE |
38 PTE_BLOCK_PXN | PTE_BLOCK_UXN
39 }, {
40 .virt = 0x80000000UL,
41 .phys = 0x80000000UL,
42 .size = 0xff80000000UL,
43 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
44 PTE_BLOCK_INNER_SHARE
45 }, {
46
47 0,
48 }
49};
50
51struct mm_region *mem_map = vexpress64_mem_map;
52
53
54
55
56__weak void vexpress64_pcie_init(void)
57{
58}
59
60int board_init(void)
61{
62 vexpress64_pcie_init();
63 return 0;
64}
65
66int dram_init(void)
67{
68 gd->ram_size = PHYS_SDRAM_1_SIZE;
69 return 0;
70}
71
72int dram_init_banksize(void)
73{
74 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
75 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
76#ifdef PHYS_SDRAM_2
77 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
78 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
79#endif
80
81 return 0;
82}
83
84
85
86
87void reset_cpu(ulong addr)
88{
89}
90
91
92
93
94int board_eth_init(bd_t *bis)
95{
96 int rc = 0;
97#ifdef CONFIG_SMC91111
98 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
99#endif
100#ifdef CONFIG_SMC911X
101 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
102#endif
103 return rc;
104}
105