LXR uboot/board/freescale/mpc8569mds/ddr.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright 2009 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7
   8#include <fsl_ddr_sdram.h>
   9#include <fsl_ddr_dimm_params.h>
  10
  11void fsl_ddr_board_options(memctl_options_t *popts,
  12                                dimm_params_t *pdimm,
  13                                unsigned int ctrl_num)
  14{
  15        /*
  16         * Factors to consider for clock adjust:
  17         *      - number of chips on bus
  18         *      - position of slot
  19         *      - DDR1 vs. DDR2?
  20         *      - ???
  21         *
  22         * This needs to be determined on a board-by-board basis.
  23         *      0110    3/4 cycle late
  24         *      0111    7/8 cycle late
  25         */
  26        popts->clk_adjust = 4;
  27
  28        /*
  29         * Factors to consider for CPO:
  30         *      - frequency
  31         *      - ddr1 vs. ddr2
  32         */
  33        popts->cpo_override = 0xff;
  34
  35        /*
  36         * Factors to consider for write data delay:
  37         *      - number of DIMMs
  38         *
  39         * 1 = 1/4 clock delay
  40         * 2 = 1/2 clock delay
  41         * 3 = 3/4 clock delay
  42         * 4 = 1   clock delay
  43         * 5 = 5/4 clock delay
  44         * 6 = 3/2 clock delay
  45         */
  46        popts->write_data_delay = 2;
  47
  48        /*
  49         * Enable half drive strength
  50         */
  51        popts->half_strength_driver_enable = 1;
  52
  53        /* Write leveling override */
  54        popts->wrlvl_en = 1;
  55        popts->wrlvl_override = 1;
  56        popts->wrlvl_sample = 0xa;
  57        popts->wrlvl_start = 0x4;
  58
  59        /* Rtt and Rtt_W override */
  60        popts->rtt_override = 1;
  61        popts->rtt_override_value = DDR3_RTT_60_OHM;
  62        popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
  63}
  64