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6#include <common.h>
7#include <command.h>
8#include <env.h>
9#include <init.h>
10#include <pci.h>
11#include <asm/processor.h>
12#include <asm/mmu.h>
13#include <asm/cache.h>
14#include <asm/immap_85xx.h>
15#include <asm/fsl_pci.h>
16#include <fsl_ddr_sdram.h>
17#include <asm/io.h>
18#include <asm/fsl_serdes.h>
19#include <miiphy.h>
20#include <linux/libfdt.h>
21#include <fdt_support.h>
22#include <tsec.h>
23#include <fsl_mdio.h>
24#include <netdev.h>
25
26#include "../common/sgmii_riser.h"
27
28int checkboard (void)
29{
30 u8 vboot;
31 u8 *pixis_base = (u8 *)PIXIS_BASE;
32
33 printf("Board: MPC8572DS Sys ID: 0x%02x, "
34 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
35 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
36 in_8(pixis_base + PIXIS_PVER));
37
38 vboot = in_8(pixis_base + PIXIS_VBOOT);
39 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
40 case PIXIS_VBOOT_LBMAP_NOR0:
41 puts ("vBank: 0\n");
42 break;
43 case PIXIS_VBOOT_LBMAP_PJET:
44 puts ("Promjet\n");
45 break;
46 case PIXIS_VBOOT_LBMAP_NAND:
47 puts ("NAND\n");
48 break;
49 case PIXIS_VBOOT_LBMAP_NOR1:
50 puts ("vBank: 1\n");
51 break;
52 }
53
54 return 0;
55}
56
57
58#if !defined(CONFIG_SPD_EEPROM)
59
60
61
62
63phys_size_t fixed_sdram (void)
64{
65 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
66 struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
67 uint d_init;
68
69 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
70 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
71
72 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
73 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
74 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
75 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
76 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
77 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
78 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
79 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
80 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
81 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
82
83#if defined (CONFIG_DDR_ECC)
84 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
85 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
86 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
87#endif
88 asm("sync;isync");
89
90 udelay(500);
91
92 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
93
94#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
95 d_init = 1;
96 debug("DDR - 1st controller: memory initializing\n");
97
98
99
100
101 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
102 udelay(1000);
103 }
104 debug("DDR: memory initialized\n\n");
105 asm("sync; isync");
106 udelay(500);
107#endif
108
109 return 512 * 1024 * 1024;
110}
111
112#endif
113
114#ifdef CONFIG_PCI
115void pci_init_board(void)
116{
117 struct pci_controller *hose;
118
119 fsl_pcie_init_board(0);
120
121 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
122
123 if (hose) {
124 u32 temp32;
125 u8 uli_busno = hose->first_busno + 2;
126
127
128
129
130
131
132 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
133 PCI_BASE_ADDRESS_1, &temp32);
134
135 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
136 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
137 temp32, 4, 0);
138 debug(" uli1572 read to %p\n", p);
139 in_be32(p);
140 }
141 }
142}
143#endif
144
145int board_early_init_r(void)
146{
147 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
148 int flash_esel = find_tlb_idx((void *)flashbase, 1);
149
150
151
152
153
154
155
156 flush_dcache();
157 invalidate_icache();
158
159 if (flash_esel == -1) {
160
161 puts("Error: Could not find TLB for FLASH BASE\n");
162 flash_esel = 2;
163 } else {
164
165 disable_tlb(flash_esel);
166 }
167
168 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
169 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
170 0, flash_esel, BOOKE_PAGESZ_256M, 1);
171
172 return 0;
173}
174
175int board_eth_init(bd_t *bis)
176{
177#ifdef CONFIG_TSEC_ENET
178 struct fsl_pq_mdio_info mdio_info;
179 struct tsec_info_struct tsec_info[4];
180 int num = 0;
181
182#ifdef CONFIG_TSEC1
183 SET_STD_TSEC_INFO(tsec_info[num], 1);
184 if (is_serdes_configured(SGMII_TSEC1)) {
185 puts("eTSEC1 is in sgmii mode.\n");
186 tsec_info[num].flags |= TSEC_SGMII;
187 }
188 num++;
189#endif
190#ifdef CONFIG_TSEC2
191 SET_STD_TSEC_INFO(tsec_info[num], 2);
192 if (is_serdes_configured(SGMII_TSEC2)) {
193 puts("eTSEC2 is in sgmii mode.\n");
194 tsec_info[num].flags |= TSEC_SGMII;
195 }
196 num++;
197#endif
198#ifdef CONFIG_TSEC3
199 SET_STD_TSEC_INFO(tsec_info[num], 3);
200 if (is_serdes_configured(SGMII_TSEC3)) {
201 puts("eTSEC3 is in sgmii mode.\n");
202 tsec_info[num].flags |= TSEC_SGMII;
203 }
204 num++;
205#endif
206#ifdef CONFIG_TSEC4
207 SET_STD_TSEC_INFO(tsec_info[num], 4);
208 if (is_serdes_configured(SGMII_TSEC4)) {
209 puts("eTSEC4 is in sgmii mode.\n");
210 tsec_info[num].flags |= TSEC_SGMII;
211 }
212 num++;
213#endif
214
215 if (!num) {
216 printf("No TSECs initialized\n");
217
218 return 0;
219 }
220
221#ifdef CONFIG_FSL_SGMII_RISER
222 fsl_sgmii_riser_init(tsec_info, num);
223#endif
224
225 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
226 mdio_info.name = DEFAULT_MII_NAME;
227 fsl_pq_mdio_init(bis, &mdio_info);
228
229 tsec_eth_init(bis, tsec_info, num);
230#endif
231
232 return pci_eth_init(bis);
233}
234
235#if defined(CONFIG_OF_BOARD_SETUP)
236int ft_board_setup(void *blob, bd_t *bd)
237{
238 phys_addr_t base;
239 phys_size_t size;
240
241 ft_cpu_setup(blob, bd);
242
243 base = env_get_bootm_low();
244 size = env_get_bootm_size();
245
246 fdt_fixup_memory(blob, (u64)base, (u64)size);
247
248 FT_FSL_PCI_SETUP;
249
250#ifdef CONFIG_FSL_SGMII_RISER
251 fsl_sgmii_riser_fdt_fixup(blob);
252#endif
253
254 return 0;
255}
256#endif
257
