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8#include <common.h>
9#include <init.h>
10#include <asm/io.h>
11#include <linux/errno.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/iomux-mx35.h>
16#include <i2c.h>
17#include <power/pmic.h>
18#include <fsl_pmic.h>
19#include <mmc.h>
20#include <fsl_esdhc_imx.h>
21#include <mc9sdz60.h>
22#include <mc13892.h>
23#include <linux/types.h>
24#include <asm/gpio.h>
25#include <asm/arch/sys_proto.h>
26#include <netdev.h>
27#include <asm/mach-types.h>
28
29#ifndef CONFIG_BOARD_LATE_INIT
30#error "CONFIG_BOARD_LATE_INIT must be set for this board"
31#endif
32
33#ifndef CONFIG_BOARD_EARLY_INIT_F
34#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
35#endif
36
37DECLARE_GLOBAL_DATA_PTR;
38
39int dram_init(void)
40{
41 u32 size1, size2;
42
43 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
44 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
45
46 gd->ram_size = size1 + size2;
47
48 return 0;
49}
50
51int dram_init_banksize(void)
52{
53 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
54 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
55
56 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
57 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
58
59 return 0;
60}
61
62#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
63
64static void setup_iomux_i2c(void)
65{
66 static const iomux_v3_cfg_t i2c1_pads[] = {
67 NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
68 NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
69 };
70
71
72 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
73}
74
75
76static void setup_iomux_spi(void)
77{
78 static const iomux_v3_cfg_t spi_pads[] = {
79 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
80 MX35_PAD_CSPI1_MISO__CSPI1_MISO,
81 MX35_PAD_CSPI1_SS0__CSPI1_SS0,
82 MX35_PAD_CSPI1_SS1__CSPI1_SS1,
83 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
84 };
85
86 imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
87}
88
89#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
90 PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
91#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
92
93static void setup_iomux_usbotg(void)
94{
95 static const iomux_v3_cfg_t usbotg_pads[] = {
96 NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
97 USBOTG_OUT_PAD_CTRL),
98 NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
99 USBOTG_IN_PAD_CTRL),
100 };
101
102
103 imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
104}
105
106#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
107
108static void setup_iomux_fec(void)
109{
110 static const iomux_v3_cfg_t fec_pads[] = {
111 NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
112 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
113 NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
114 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
115 NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
116 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
117 NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
118 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
119 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
120 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
121 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
122 NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
123 NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
124 NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
125 PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
126 NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
127 NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
128 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
129 NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
130 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
131 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
132 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
133 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
134 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
135 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
136 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
137 NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
138 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
139 NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
140 };
141
142
143 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
144}
145
146int board_early_init_f(void)
147{
148 struct ccm_regs *ccm =
149 (struct ccm_regs *)IMX_CCM_BASE;
150
151
152 writel(readl(&ccm->cgr0) |
153 MXC_CCM_CGR0_EMI_MASK |
154 MXC_CCM_CGR0_EDIO_MASK |
155 MXC_CCM_CGR0_EPIT1_MASK,
156 &ccm->cgr0);
157
158 writel(readl(&ccm->cgr1) |
159 MXC_CCM_CGR1_FEC_MASK |
160 MXC_CCM_CGR1_GPIO1_MASK |
161 MXC_CCM_CGR1_GPIO2_MASK |
162 MXC_CCM_CGR1_GPIO3_MASK |
163 MXC_CCM_CGR1_I2C1_MASK |
164 MXC_CCM_CGR1_I2C2_MASK |
165 MXC_CCM_CGR1_IPU_MASK,
166 &ccm->cgr1);
167
168
169 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
170
171 setup_iomux_i2c();
172 setup_iomux_usbotg();
173 setup_iomux_fec();
174 setup_iomux_spi();
175
176 return 0;
177}
178
179int board_init(void)
180{
181 gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS;
182
183 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
184
185 return 0;
186}
187
188static inline int pmic_detect(void)
189{
190 unsigned int id;
191 struct pmic *p = pmic_get("FSL_PMIC");
192 if (!p)
193 return -ENODEV;
194
195 pmic_reg_read(p, REG_IDENTIFICATION, &id);
196
197 id = (id >> 6) & 0x7;
198 if (id == 0x7)
199 return 1;
200 return 0;
201}
202
203u32 get_board_rev(void)
204{
205 int rev;
206
207 rev = pmic_detect();
208
209 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
210}
211
212int board_late_init(void)
213{
214 u8 val;
215 u32 pmic_val;
216 struct pmic *p;
217 int ret;
218
219 ret = pmic_init(I2C_0);
220 if (ret)
221 return ret;
222
223 if (pmic_detect()) {
224 p = pmic_get("FSL_PMIC");
225 imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
226
227 pmic_reg_read(p, REG_SETTING_0, &pmic_val);
228 pmic_reg_write(p, REG_SETTING_0,
229 pmic_val | VO_1_30V | VO_1_50V);
230 pmic_reg_read(p, REG_MODE_0, &pmic_val);
231 pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
232
233 imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
234
235 gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
236 }
237
238 val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
239 mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
240 mdelay(200);
241
242 val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
243 mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
244 mdelay(200);
245
246 val |= 0x80;
247 mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
248
249
250 printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
251
252 return 0;
253}
254
255int board_eth_init(bd_t *bis)
256{
257#if defined(CONFIG_SMC911X)
258 int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
259 if (rc)
260 return rc;
261#endif
262 return cpu_eth_init(bis);
263}
264
265#if defined(CONFIG_FSL_ESDHC_IMX)
266
267struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
268
269int board_mmc_init(bd_t *bis)
270{
271 static const iomux_v3_cfg_t sdhc1_pads[] = {
272 MX35_PAD_SD1_CMD__ESDHC1_CMD,
273 MX35_PAD_SD1_CLK__ESDHC1_CLK,
274 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
275 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
276 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
277 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
278 };
279
280
281 imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
282
283 esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
284 return fsl_esdhc_initialize(bis, &esdhc_cfg);
285}
286
287int board_mmc_getcd(struct mmc *mmc)
288{
289 return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
290}
291#endif
292
