1/* SPDX-License-Identifier: GPL-2.0+ */ 2/** 3 * Copyright 2013 Freescale Semiconductor 4 * 5 * This file provides support for the ngPIXIS, a board-specific FPGA used on 6 * some Freescale reference boards. 7 */ 8 9/* 10 * CPLD register set. Feel free to add board-specific #ifdefs where necessary. 11 */ 12struct cpld_data { 13 u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ 14 u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ 15 u8 hw_ver; /* 0x02 - Hardware Revision Register */ 16 u8 sw_ver; /* 0x03 - Software Revision register */ 17 u8 res0[12]; /* 0x04 - 0x0F - not used */ 18 u8 reset_ctl1; /* 0x10 - Reset control Register1 */ 19 u8 reset_ctl2; /* 0x11 - Reset control Register2 */ 20 u8 int_status; /* 0x12 - Interrupt status Register */ 21 u8 flash_ctl_status; /* 0x13 - Flash control and status register */ 22 u8 fan_ctl_status; /* 0x14 - Fan control and status register */ 23#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 24 u8 int_mask; /* 0x15 - Interrupt mask Register */ 25#else 26 u8 led_ctl_status; /* 0x15 - LED control and status register */ 27#endif 28 u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ 29 u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ 30 u8 boot_override; /* 0x18 - Boot override register */ 31 u8 boot_config1; /* 0x19 - Boot config override register*/ 32 u8 boot_config2; /* 0x1A - Boot config override register*/ 33} cpld_data_t; 34 35 36/* Pointer to the CPLD register set */ 37 38u8 cpld_read(unsigned int reg); 39void cpld_write(unsigned int reg, u8 value); 40 41#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 42#define CPLD_WRITE(reg, value)\ 43 cpld_write(offsetof(struct cpld_data, reg), value) 44#define MISC_CTL_SG_SEL 0x80 45#define MISC_CTL_AURORA_SEL 0x02 46#define MISC_MUX_QE_TDM 0xc0 47