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8#include <init.h>
9#include <asm/arch/clock.h>
10#include <asm/arch/imx-regs.h>
11#include <asm/arch/iomux.h>
12#include <asm/arch/mx6-pins.h>
13#include <env.h>
14#include <linux/errno.h>
15#include <linux/libfdt.h>
16#include <asm/gpio.h>
17#include <asm/mach-imx/mxc_i2c.h>
18#include <asm/mach-imx/iomux-v3.h>
19#include <asm/mach-imx/boot_mode.h>
20#include <asm/mach-imx/video.h>
21#include <mmc.h>
22#include <fsl_esdhc_imx.h>
23#include <miiphy.h>
24#include <net.h>
25#include <netdev.h>
26#include <asm/arch/mxc_hdmi.h>
27#include <asm/arch/crm_regs.h>
28#include <asm/io.h>
29#include <asm/arch/sys_proto.h>
30#include <i2c.h>
31#include <input.h>
32#include <pwm.h>
33#include <version.h>
34#include <stdlib.h>
35#include "../common/ge_common.h"
36#include "../common/vpd_reader.h"
37#include "../../../drivers/net/e1000.h"
38DECLARE_GLOBAL_DATA_PTR;
39
40static int confidx = 3;
41static struct vpd_cache vpd;
42
43#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
45 PAD_CTL_HYS)
46
47#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
49 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50
51#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
52 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
53
54#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
56
57#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
58 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
59
60#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
62 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
63
64#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
65
66int dram_init(void)
67{
68 gd->ram_size = imx_ddr_size();
69
70 return 0;
71}
72
73static iomux_v3_cfg_t const uart3_pads[] = {
74 MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
75 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
76 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
77 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
78};
79
80static iomux_v3_cfg_t const uart4_pads[] = {
81 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
82 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
83};
84
85static iomux_v3_cfg_t const enet_pads[] = {
86 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
95 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
96 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
97 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
98 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
99 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
100 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
101
102 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
103};
104
105static void setup_iomux_enet(void)
106{
107 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
108
109
110 gpio_request(IMX_GPIO_NR(1, 28), "fec_rst");
111 gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
112 mdelay(10);
113 gpio_set_value(IMX_GPIO_NR(1, 28), 1);
114 mdelay(1);
115}
116
117static struct i2c_pads_info i2c_pad_info1 = {
118 .scl = {
119 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
120 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
121 .gp = IMX_GPIO_NR(5, 27)
122 },
123 .sda = {
124 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
125 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
126 .gp = IMX_GPIO_NR(5, 26)
127 }
128};
129
130static struct i2c_pads_info i2c_pad_info2 = {
131 .scl = {
132 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
133 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
134 .gp = IMX_GPIO_NR(4, 12)
135 },
136 .sda = {
137 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
138 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
139 .gp = IMX_GPIO_NR(4, 13)
140 }
141};
142
143static struct i2c_pads_info i2c_pad_info3 = {
144 .scl = {
145 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
146 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
147 .gp = IMX_GPIO_NR(1, 3)
148 },
149 .sda = {
150 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
151 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
152 .gp = IMX_GPIO_NR(1, 6)
153 }
154};
155
156static iomux_v3_cfg_t const pcie_pads[] = {
157 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
158 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
159};
160
161static void setup_pcie(void)
162{
163 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
164}
165
166static void setup_iomux_uart(void)
167{
168 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
169 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
170}
171
172static int mx6_rgmii_rework(struct phy_device *phydev)
173{
174
175
176 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
177
178 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
179
180 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
181
182 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
183
184
185
186 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
187
188
189 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
190
191 return 0;
192}
193
194int board_phy_config(struct phy_device *phydev)
195{
196 mx6_rgmii_rework(phydev);
197
198 if (phydev->drv->config)
199 phydev->drv->config(phydev);
200
201 return 0;
202}
203
204#if defined(CONFIG_VIDEO_IPUV3)
205static iomux_v3_cfg_t const backlight_pads[] = {
206
207 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
208#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
209
210 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
211#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
212
213 MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
214};
215
216static void do_enable_hdmi(struct display_info_t const *dev)
217{
218 imx_enable_hdmi_phy();
219}
220
221int board_cfb_skip(void)
222{
223 gpio_direction_output(LVDS_POWER_GP, 1);
224
225 return 0;
226}
227
228static int is_b850v3(void)
229{
230 return confidx == 3;
231}
232
233static int detect_lcd(struct display_info_t const *dev)
234{
235 return !is_b850v3();
236}
237
238struct display_info_t const displays[] = {{
239 .bus = -1,
240 .addr = -1,
241 .pixfmt = IPU_PIX_FMT_RGB24,
242 .detect = detect_lcd,
243 .enable = NULL,
244 .mode = {
245 .name = "G121X1-L03",
246 .refresh = 60,
247 .xres = 1024,
248 .yres = 768,
249 .pixclock = 15385,
250 .left_margin = 20,
251 .right_margin = 300,
252 .upper_margin = 30,
253 .lower_margin = 8,
254 .hsync_len = 1,
255 .vsync_len = 1,
256 .sync = FB_SYNC_EXT,
257 .vmode = FB_VMODE_NONINTERLACED
258} }, {
259 .bus = -1,
260 .addr = 3,
261 .pixfmt = IPU_PIX_FMT_RGB24,
262 .detect = detect_hdmi,
263 .enable = do_enable_hdmi,
264 .mode = {
265 .name = "HDMI",
266 .refresh = 60,
267 .xres = 1024,
268 .yres = 768,
269 .pixclock = 15385,
270 .left_margin = 220,
271 .right_margin = 40,
272 .upper_margin = 21,
273 .lower_margin = 7,
274 .hsync_len = 60,
275 .vsync_len = 10,
276 .sync = FB_SYNC_EXT,
277 .vmode = FB_VMODE_NONINTERLACED
278} } };
279size_t display_count = ARRAY_SIZE(displays);
280
281static void enable_videopll(void)
282{
283 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
284 s32 timeout = 100000;
285
286 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
287
288
289
290
291
292
293
294
295
296
297
298
299 clrsetbits_le32(&ccm->analog_pll_video,
300 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
301 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
302 BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
303 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
304
305 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
306 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
307
308 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
309
310 while (timeout--)
311 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
312 break;
313
314 if (timeout < 0)
315 printf("Warning: video pll lock timeout!\n");
316
317 clrsetbits_le32(&ccm->analog_pll_video,
318 BM_ANADIG_PLL_VIDEO_BYPASS,
319 BM_ANADIG_PLL_VIDEO_ENABLE);
320}
321
322static void setup_display_b850v3(void)
323{
324 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
325 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
326
327 enable_videopll();
328
329
330 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
331
332 imx_setup_hdmi();
333
334
335 clrsetbits_le32(&mxc_ccm->chsccdr,
336 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
337 (CHSCCDR_CLK_SEL_LDB_DI0 <<
338 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
339
340
341 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
342
343 enable_ipu_clock();
344
345 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
346 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
347 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
348 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
349 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
350 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
351 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
352 IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
353 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
354 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
355 &iomux->gpr[2]);
356
357 clrbits_le32(&iomux->gpr[3],
358 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
359 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
360 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
361}
362
363static void setup_display_bx50v3(void)
364{
365 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
366 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
367
368 enable_videopll();
369
370
371
372
373
374
375 mdelay(200);
376
377
378 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
379
380
381 clrsetbits_le32(&mxc_ccm->chsccdr,
382 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
383 (CHSCCDR_CLK_SEL_LDB_DI0 <<
384 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
385
386
387 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
388
389 enable_ipu_clock();
390
391 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
392 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
393 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
394 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
395 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
396 &iomux->gpr[2]);
397
398 clrsetbits_le32(&iomux->gpr[3],
399 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
400 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
401 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
402
403
404 imx_iomux_v3_setup_multiple_pads(backlight_pads,
405 ARRAY_SIZE(backlight_pads));
406 gpio_request(LVDS_POWER_GP, "lvds_power");
407 gpio_direction_input(LVDS_POWER_GP);
408}
409#endif
410
411
412
413
414
415int overwrite_console(void)
416{
417 return 1;
418}
419
420#define VPD_TYPE_INVALID 0x00
421#define VPD_BLOCK_NETWORK 0x20
422#define VPD_BLOCK_HWID 0x44
423#define VPD_PRODUCT_B850 1
424#define VPD_PRODUCT_B650 2
425#define VPD_PRODUCT_B450 3
426#define VPD_HAS_MAC1 0x1
427#define VPD_HAS_MAC2 0x2
428#define VPD_MAC_ADDRESS_LENGTH 6
429
430struct vpd_cache {
431 bool is_read;
432 u8 product_id;
433 u8 has;
434 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
435 unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
436};
437
438
439
440
441static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
442 size_t size, u8 const *data)
443{
444 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
445 size >= 1) {
446 vpd->product_id = data[0];
447 } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
448 type != VPD_TYPE_INVALID) {
449 if (size >= 6) {
450 vpd->has |= VPD_HAS_MAC1;
451 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
452 }
453 if (size >= 12) {
454 vpd->has |= VPD_HAS_MAC2;
455 memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
456 }
457 }
458
459 return 0;
460}
461
462static void process_vpd(struct vpd_cache *vpd)
463{
464 int fec_index = -1;
465 int i210_index = -1;
466
467 if (!vpd->is_read) {
468 printf("VPD wasn't read");
469 return;
470 }
471
472 switch (vpd->product_id) {
473 case VPD_PRODUCT_B450:
474 env_set("confidx", "1");
475 i210_index = 0;
476 fec_index = 1;
477 break;
478 case VPD_PRODUCT_B650:
479 env_set("confidx", "2");
480 i210_index = 0;
481 fec_index = 1;
482 break;
483 case VPD_PRODUCT_B850:
484 env_set("confidx", "3");
485 i210_index = 1;
486 fec_index = 2;
487 break;
488 }
489
490 if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
491 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
492
493 if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
494 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
495}
496
497int board_eth_init(bd_t *bis)
498{
499 setup_iomux_enet();
500 setup_pcie();
501
502 e1000_initialize(bis);
503
504 return cpu_eth_init(bis);
505}
506
507static iomux_v3_cfg_t const misc_pads[] = {
508 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
509 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
510 MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
511 MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
512 MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
513 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
514 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
515 MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
516};
517#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
518#define WIFI_EN IMX_GPIO_NR(6, 14)
519
520int board_early_init_f(void)
521{
522 imx_iomux_v3_setup_multiple_pads(misc_pads,
523 ARRAY_SIZE(misc_pads));
524
525 setup_iomux_uart();
526
527#if defined(CONFIG_VIDEO_IPUV3)
528
529 select_ldb_di_clock_source(MXC_PLL5_CLK);
530#endif
531 return 0;
532}
533
534static void set_confidx(const struct vpd_cache* vpd)
535{
536 switch (vpd->product_id) {
537 case VPD_PRODUCT_B450:
538 confidx = 1;
539 break;
540 case VPD_PRODUCT_B650:
541 confidx = 2;
542 break;
543 case VPD_PRODUCT_B850:
544 confidx = 3;
545 break;
546 }
547}
548
549int board_init(void)
550{
551 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
552 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
553 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
554
555 if (!read_vpd(&vpd, vpd_callback)) {
556 vpd.is_read = true;
557 set_confidx(&vpd);
558 }
559
560 gpio_request(SUS_S3_OUT, "sus_s3_out");
561 gpio_direction_output(SUS_S3_OUT, 1);
562
563 gpio_request(WIFI_EN, "wifi_en");
564 gpio_direction_output(WIFI_EN, 1);
565
566#if defined(CONFIG_VIDEO_IPUV3)
567 if (is_b850v3())
568 setup_display_b850v3();
569 else
570 setup_display_bx50v3();
571
572 gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
573 gpio_direction_input(LVDS_BACKLIGHT_GP);
574#endif
575
576
577 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
578
579 return 0;
580}
581
582#ifdef CONFIG_CMD_BMODE
583static const struct boot_mode board_boot_modes[] = {
584
585 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
586 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
587 {NULL, 0},
588};
589#endif
590
591void pmic_init(void)
592{
593#define I2C_PMIC 0x2
594#define DA9063_I2C_ADDR 0x58
595#define DA9063_REG_BCORE2_CFG 0x9D
596#define DA9063_REG_BCORE1_CFG 0x9E
597#define DA9063_REG_BPRO_CFG 0x9F
598#define DA9063_REG_BIO_CFG 0xA0
599#define DA9063_REG_BMEM_CFG 0xA1
600#define DA9063_REG_BPERI_CFG 0xA2
601#define DA9063_BUCK_MODE_MASK 0xC0
602#define DA9063_BUCK_MODE_MANUAL 0x00
603#define DA9063_BUCK_MODE_SLEEP 0x40
604#define DA9063_BUCK_MODE_SYNC 0x80
605#define DA9063_BUCK_MODE_AUTO 0xC0
606
607 uchar val;
608
609 i2c_set_bus_num(I2C_PMIC);
610
611 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
612 val &= ~DA9063_BUCK_MODE_MASK;
613 val |= DA9063_BUCK_MODE_SYNC;
614 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
615
616 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
617 val &= ~DA9063_BUCK_MODE_MASK;
618 val |= DA9063_BUCK_MODE_SYNC;
619 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
620
621 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
622 val &= ~DA9063_BUCK_MODE_MASK;
623 val |= DA9063_BUCK_MODE_SYNC;
624 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
625
626 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
627 val &= ~DA9063_BUCK_MODE_MASK;
628 val |= DA9063_BUCK_MODE_SYNC;
629 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
630
631 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
632 val &= ~DA9063_BUCK_MODE_MASK;
633 val |= DA9063_BUCK_MODE_SYNC;
634 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
635
636 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
637 val &= ~DA9063_BUCK_MODE_MASK;
638 val |= DA9063_BUCK_MODE_SYNC;
639 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
640}
641
642int board_late_init(void)
643{
644 process_vpd(&vpd);
645
646#ifdef CONFIG_CMD_BMODE
647 add_board_boot_modes(board_boot_modes);
648#endif
649
650 if (is_b850v3())
651 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
652 else
653 env_set("videoargs", "video=LVDS-1:1024x768@65");
654
655
656 pmic_init();
657
658 check_time();
659
660 return 0;
661}
662
663
664
665
666
667
668static void remove_ethaddr_env_var(int index)
669{
670 char env_var_name[9];
671
672 sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
673 env_set(env_var_name, NULL);
674}
675
676int last_stage_init(void)
677{
678 int i;
679
680
681
682
683
684 for (i = 0; i < 3; ++i)
685 remove_ethaddr_env_var(i);
686
687 return 0;
688}
689
690int checkboard(void)
691{
692 printf("BOARD: %s\n", CONFIG_BOARD_NAME);
693 return 0;
694}
695
696#ifdef CONFIG_OF_BOARD_SETUP
697int ft_board_setup(void *blob, bd_t *bd)
698{
699 fdt_setprop(blob, 0, "ge,boot-ver", version_string,
700 strlen(version_string) + 1);
701 return 0;
702}
703#endif
704
705static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
706{
707#ifdef CONFIG_VIDEO_IPUV3
708
709
710 mdelay(250);
711
712
713 pwm_init(0, 0, 0);
714
715
716 pwm_config(0, 5000000, 5000000);
717
718
719 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
720
721 pwm_enable(0);
722#endif
723
724 return 0;
725}
726
727U_BOOT_CMD(
728 bx50_backlight_enable, 1, 1, do_backlight_enable,
729 "enable Bx50 backlight",
730 ""
731);
732
