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8#include <common.h>
9#include <malloc.h>
10#include <dm/platform_data/serial_sh.h>
11#include <asm/processor.h>
12#include <asm/mach-types.h>
13#include <asm/io.h>
14#include <linux/errno.h>
15#include <asm/arch/sys_proto.h>
16#include <asm/gpio.h>
17#include <asm/arch/rmobile.h>
18#include <asm/arch/rcar-mstp.h>
19
20#include <spl.h>
21
22#define TMU0_MSTP125 BIT(25)
23#define SCIFA0_MSTP204 BIT(4)
24#define QSPI_MSTP917 BIT(17)
25
26#define SD2CKCR 0xE615026C
27#define SD_97500KHZ 0x7
28
29struct reg_config {
30 u16 off;
31 u32 val;
32};
33
34static void dbsc_wait(u16 reg)
35{
36 static const u32 dbsc3_0_base = DBSC3_0_BASE;
37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
38
39 while (!(readl(dbsc3_0_base + reg) & BIT(0)))
40 ;
41
42 while (!(readl(dbsc3_1_base + reg) & BIT(0)))
43 ;
44}
45
46static void spl_init_sys(void)
47{
48 u32 r0 = 0;
49
50 writel(0xa5a5a500, 0xe6020004);
51 writel(0xa5a5a500, 0xe6030004);
52
53 asm volatile(
54
55 "mcr 15, 0, %0, cr7, cr5, 0 \n"
56
57 "mcr 15, 0, %0, cr7, cr5, 6 \n"
58
59 "mrc 15, 0, %0, cr1, cr0, 0 \n"
60 "orr %0, #0x1800 \n"
61 "mcr 15, 0, %0, cr1, cr0, 0 \n"
62 "isb sy \n"
63 :"=r"(r0));
64}
65
66static void spl_init_pfc(void)
67{
68 static const struct reg_config pfc_with_unlock[] = {
69 { 0x0090, 0x00140300 },
70 { 0x0094, 0x09500000 },
71 { 0x0098, 0xc0000084 },
72 { 0x0020, 0x01a33492 },
73 { 0x0024, 0x10000000 },
74 { 0x0028, 0x08449252 },
75 { 0x002c, 0x2925b322 },
76 { 0x0030, 0x0c311249 },
77 { 0x0034, 0x10124000 },
78 { 0x0038, 0x00001295 },
79 { 0x003c, 0x50890000 },
80 { 0x0040, 0x0eaa56aa },
81 { 0x0044, 0x55550000 },
82 { 0x0048, 0x00000005 },
83 { 0x004c, 0x54800000 },
84 { 0x0050, 0x3736db55 },
85 { 0x0054, 0x29148da3 },
86 { 0x0058, 0x48c446e1 },
87 { 0x005c, 0x2a3a54dc },
88 { 0x0160, 0x00000023 },
89 { 0x0004, 0xfca0ffff },
90 { 0x0008, 0x3fbffbf0 },
91 { 0x000c, 0x3ffdffff },
92 { 0x0010, 0x00ffffff },
93 { 0x0014, 0xfc3ffff3 },
94 { 0x0018, 0xe4fdfff7 },
95 };
96
97 static const struct reg_config pfc_without_unlock[] = {
98 { 0x0104, 0xffffbfff },
99 { 0x0108, 0xb1ffffe1 },
100 { 0x010c, 0xffffffff },
101 { 0x0110, 0xffffffff },
102 { 0x0114, 0xe047beab },
103 { 0x0118, 0x00000203 },
104 };
105
106 static const u32 pfc_base = 0xe6060000;
107
108 unsigned int i;
109
110 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
111 writel(~pfc_with_unlock[i].val, pfc_base);
112 writel(pfc_with_unlock[i].val,
113 pfc_base | pfc_with_unlock[i].off);
114 }
115
116 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
117 writel(pfc_without_unlock[i].val,
118 pfc_base | pfc_without_unlock[i].off);
119}
120
121static void spl_init_gpio(void)
122{
123 static const u16 gpio_offs[] = {
124 0x1000, 0x3000, 0x4000, 0x5000
125 };
126
127 static const struct reg_config gpio_set[] = {
128 { 0x4000, 0x00c00000 },
129 { 0x5000, 0x63020000 },
130 };
131
132 static const struct reg_config gpio_clr[] = {
133 { 0x1000, 0x00000000 },
134 { 0x3000, 0x00000000 },
135 { 0x4000, 0x00c00000 },
136 { 0x5000, 0xe3020000 },
137 };
138
139 static const u32 gpio_base = 0xe6050000;
140
141 unsigned int i;
142
143 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
144 writel(0, gpio_base | 0x20 | gpio_offs[i]);
145
146 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
147 writel(0, gpio_base | 0x00 | gpio_offs[i]);
148
149 for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
150 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
151
152 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
153 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
154}
155
156static void spl_init_lbsc(void)
157{
158 static const struct reg_config lbsc_config[] = {
159 { 0x00, 0x00000020 },
160 { 0x08, 0x00002020 },
161 { 0x30, 0x02150326 },
162 { 0x38, 0x077f077f },
163 };
164
165 static const u16 lbsc_offs[] = {
166 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
167 };
168
169 static const u32 lbsc_base = 0xfec00200;
170
171 unsigned int i;
172
173 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
174 writel(lbsc_config[i].val,
175 lbsc_base | lbsc_config[i].off);
176 writel(lbsc_config[i].val,
177 lbsc_base | (lbsc_config[i].off + 4));
178 }
179
180 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
181 writel(0, lbsc_base | lbsc_offs[i]);
182}
183
184static void spl_init_dbsc(void)
185{
186 static const struct reg_config dbsc_config1[] = {
187 { 0x0280, 0x0000a55a },
188 { 0x0018, 0x21000000 },
189 { 0x0018, 0x11000000 },
190 { 0x0018, 0x10000000 },
191 { 0x0290, 0x00000001 },
192 { 0x02a0, 0x80000000 },
193 { 0x0290, 0x00000004 },
194 };
195
196 static const struct reg_config dbsc_config2[] = {
197 { 0x0290, 0x00000006 },
198 { 0x02a0, 0x0001c000 },
199 };
200
201 static const struct reg_config dbsc_config3r0d0[] = {
202 { 0x0290, 0x0000000f },
203 { 0x02a0, 0x00181885 },
204 { 0x0290, 0x00000070 },
205 { 0x02a0, 0x7c000887 },
206 { 0x0290, 0x00000080 },
207 { 0x02a0, 0x7c000887 },
208 { 0x0290, 0x00000090 },
209 { 0x02a0, 0x7c000887 },
210 { 0x0290, 0x000000a0 },
211 { 0x02a0, 0x7c000887 },
212 { 0x0290, 0x000000b0 },
213 { 0x02a0, 0x7c000880 },
214 { 0x0290, 0x000000c0 },
215 { 0x02a0, 0x7c000880 },
216 { 0x0290, 0x000000d0 },
217 { 0x02a0, 0x7c000880 },
218 { 0x0290, 0x000000e0 },
219 { 0x02a0, 0x7c000880 },
220 };
221
222 static const struct reg_config dbsc_config3r0d1[] = {
223 { 0x0290, 0x0000000f },
224 { 0x02a0, 0x00181885 },
225 { 0x0290, 0x00000070 },
226 { 0x02a0, 0x7c000887 },
227 { 0x0290, 0x00000080 },
228 { 0x02a0, 0x7c000887 },
229 { 0x0290, 0x00000090 },
230 { 0x02a0, 0x7c000887 },
231 { 0x0290, 0x000000a0 },
232 { 0x02a0, 0x7c000887 },
233 };
234
235 static const struct reg_config dbsc_config3r2[] = {
236 { 0x0290, 0x0000000f },
237 { 0x02a0, 0x00181224 },
238 };
239
240 static const struct reg_config dbsc_config4[] = {
241 { 0x0290, 0x00000010 },
242 { 0x02a0, 0xf004649b },
243 { 0x0290, 0x00000061 },
244 { 0x02a0, 0x0000006d },
245 { 0x0290, 0x00000001 },
246 { 0x02a0, 0x00000073 },
247 { 0x0020, 0x00000007 },
248 { 0x0024, 0x0f030a02 },
249 { 0x0030, 0x00000001 },
250 { 0x00b0, 0x00000000 },
251 { 0x0040, 0x0000000b },
252 { 0x0044, 0x00000008 },
253 { 0x0048, 0x00000000 },
254 { 0x0050, 0x0000000b },
255 { 0x0054, 0x000c000b },
256 { 0x0058, 0x00000027 },
257 { 0x005c, 0x0000001c },
258 { 0x0060, 0x00000006 },
259 { 0x0064, 0x00000020 },
260 { 0x0068, 0x00000008 },
261 { 0x006c, 0x0000000c },
262 { 0x0070, 0x00000009 },
263 { 0x0074, 0x00000012 },
264 { 0x0078, 0x000000d0 },
265 { 0x007c, 0x00140005 },
266 { 0x0080, 0x00050004 },
267 { 0x0084, 0x70233005 },
268 { 0x0088, 0x000c0000 },
269 { 0x008c, 0x00000200 },
270 { 0x0090, 0x00000040 },
271 { 0x0100, 0x00000001 },
272 { 0x00c0, 0x00020001 },
273 { 0x00c8, 0x20042004 },
274 { 0x0380, 0x00020002 },
275 { 0x0390, 0x0000001f },
276 };
277
278 static const struct reg_config dbsc_config5[] = {
279 { 0x0244, 0x00000011 },
280 { 0x0290, 0x00000003 },
281 { 0x02a0, 0x0300c4e1 },
282 { 0x0290, 0x00000023 },
283 { 0x02a0, 0x00fcdb60 },
284 { 0x0290, 0x00000011 },
285 { 0x02a0, 0x1000040b },
286 { 0x0290, 0x00000012 },
287 { 0x02a0, 0x9d9cbb66 },
288 { 0x0290, 0x00000013 },
289 { 0x02a0, 0x1a868400 },
290 { 0x0290, 0x00000014 },
291 { 0x02a0, 0x300214d8 },
292 { 0x0290, 0x00000015 },
293 { 0x02a0, 0x00000d70 },
294 { 0x0290, 0x00000016 },
295 { 0x02a0, 0x00000006 },
296 { 0x0290, 0x00000017 },
297 { 0x02a0, 0x00000018 },
298 { 0x0290, 0x0000001a },
299 { 0x02a0, 0x910035c7 },
300 { 0x0290, 0x00000004 },
301 };
302
303 static const struct reg_config dbsc_config6[] = {
304 { 0x0290, 0x00000001 },
305 { 0x02a0, 0x00000181 },
306 { 0x0018, 0x11000000 },
307 { 0x0290, 0x00000004 },
308 };
309
310 static const struct reg_config dbsc_config7[] = {
311 { 0x0290, 0x00000001 },
312 { 0x02a0, 0x0000fe01 },
313 { 0x0304, 0x00000000 },
314 { 0x00f4, 0x01004c20 },
315 { 0x00f8, 0x014000aa },
316 { 0x00e0, 0x00000140 },
317 { 0x00e4, 0x00081860 },
318 { 0x00e8, 0x00010000 },
319 { 0x0290, 0x00000004 },
320 };
321
322 static const struct reg_config dbsc_config8[] = {
323 { 0x0014, 0x00000001 },
324 { 0x0010, 0x00000001 },
325 { 0x0280, 0x00000000 },
326 };
327
328 static const u32 dbsc3_0_base = DBSC3_0_BASE;
329 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
330 static const u32 prr_base = 0xff000044;
331 const u16 prr_rev = readl(prr_base) & 0x7fff;
332 unsigned int i;
333
334 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
335 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
336 writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
337 }
338
339 dbsc_wait(0x2a0);
340
341 for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
342 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
343 writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
344 }
345
346 if (prr_rev == 0x4500) {
347 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
348 writel(dbsc_config3r0d0[i].val,
349 dbsc3_0_base | dbsc_config3r0d0[i].off);
350 }
351 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
352 writel(dbsc_config3r0d1[i].val,
353 dbsc3_1_base | dbsc_config3r0d1[i].off);
354 }
355 } else if (prr_rev != 0x4510) {
356 for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
357 writel(dbsc_config3r2[i].val,
358 dbsc3_0_base | dbsc_config3r2[i].off);
359 writel(dbsc_config3r2[i].val,
360 dbsc3_1_base | dbsc_config3r2[i].off);
361 }
362 }
363
364 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
365 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
366 writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
367 }
368
369 dbsc_wait(0x240);
370
371 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
372 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
373 writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
374 }
375
376 dbsc_wait(0x2a0);
377
378 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
379 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
380 writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
381 }
382
383 dbsc_wait(0x2a0);
384
385 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
386 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
387 writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
388 }
389
390 dbsc_wait(0x2a0);
391
392 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
393 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
394 writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
395 }
396
397}
398
399static void spl_init_qspi(void)
400{
401 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
402
403 static const u32 qspi_base = 0xe6b10000;
404
405 writeb(0x08, qspi_base + 0x00);
406 writeb(0x00, qspi_base + 0x01);
407 writeb(0x06, qspi_base + 0x02);
408 writeb(0x01, qspi_base + 0x0a);
409 writeb(0x00, qspi_base + 0x0b);
410 writeb(0x00, qspi_base + 0x0c);
411 writeb(0x00, qspi_base + 0x0d);
412 writeb(0x00, qspi_base + 0x0e);
413
414 writew(0xe080, qspi_base + 0x10);
415
416 writeb(0xc0, qspi_base + 0x18);
417 writeb(0x00, qspi_base + 0x18);
418 writeb(0x00, qspi_base + 0x08);
419 writeb(0x48, qspi_base + 0x00);
420}
421
422void board_init_f(ulong dummy)
423{
424 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
425 mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
426
427
428
429
430
431 writel(SD_97500KHZ, SD2CKCR);
432
433 spl_init_sys();
434 spl_init_pfc();
435 spl_init_gpio();
436 spl_init_lbsc();
437 spl_init_dbsc();
438 spl_init_qspi();
439}
440
441void spl_board_init(void)
442{
443
444 preloader_console_init();
445}
446
447void board_boot_order(u32 *spl_boot_list)
448{
449 const u32 jtag_magic = 0x1337c0de;
450 const u32 load_magic = 0xb33fc0de;
451
452
453
454
455
456 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
457 printf("JTAG boot detected!\n");
458
459 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
460 ;
461
462 spl_boot_list[0] = BOOT_DEVICE_RAM;
463 spl_boot_list[1] = BOOT_DEVICE_NONE;
464
465 return;
466 }
467
468
469 spl_boot_list[0] = BOOT_DEVICE_SPI;
470 spl_boot_list[1] = BOOT_DEVICE_UART;
471 spl_boot_list[2] = BOOT_DEVICE_NONE;
472}
473
474void reset_cpu(ulong addr)
475{
476}
477
