LXR uboot/board/xilinx/zynqmp/tap

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Xilinx ZynqMP SoC Tap Delay Programming
   4 *
   5 * Copyright (C) 2018 Xilinx, Inc.
   6 */
   7
   8#include <common.h>
   9#include <zynqmp_tap_delay.h>
  10#include <asm/arch/sys_proto.h>
  11
  12#define SD_DLL_CTRL                     0xFF180358
  13#define SD_ITAP_DLY                     0xFF180314
  14#define SD_OTAP_DLY                     0xFF180318
  15#define SD0_DLL_RST_MASK                0x00000004
  16#define SD0_DLL_RST                     0x00000004
  17#define SD1_DLL_RST_MASK                0x00040000
  18#define SD1_DLL_RST                     0x00040000
  19#define SD0_ITAPCHGWIN_MASK             0x00000200
  20#define SD0_ITAPCHGWIN                  0x00000200
  21#define SD1_ITAPCHGWIN_MASK             0x02000000
  22#define SD1_ITAPCHGWIN                  0x02000000
  23#define SD0_ITAPDLYENA_MASK             0x00000100
  24#define SD0_ITAPDLYENA                  0x00000100
  25#define SD1_ITAPDLYENA_MASK             0x01000000
  26#define SD1_ITAPDLYENA                  0x01000000
  27#define SD0_ITAPDLYSEL_MASK             0x000000FF
  28
  29#define SD1_ITAPDLYSEL_MASK             0x00FF0000
  30
  31#define SD0_OTAPDLYSEL_MASK             0x0000003F
  32
  33#define SD1_OTAPDLYSEL_MASK             0x003F0000
  34
  35void zynqmp_dll_reset(u8 deviceid)
  36{
  37        /* Issue DLL Reset */
  38        if (deviceid == 0)
  39                zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
  40                                  SD0_DLL_RST);
  41        else
  42                zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
  43                                  SD1_DLL_RST);
  44
  45        mdelay(1);
  46
  47        /* Release DLL Reset */
  48        if (deviceid == 0)
  49                zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
  50        else
  51                zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
  52}
  53
  54void arasan_zynqmp_set_tapdelay(u8 deviceid, u32 itap_delay, u32 otap_delay)
  55{
  56        if (deviceid == 0) {
  57                zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
  58                                  SD0_DLL_RST);
  59                /* Program ITAP */
  60                if (itap_delay) {
  61                        zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
  62                                          SD0_ITAPCHGWIN);
  63                        zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
  64                                          SD0_ITAPDLYENA);
  65                        zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
  66                                          itap_delay);
  67                        zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
  68                                          0x0);
  69                }
  70
  71                /* Program OTAP */
  72                if (otap_delay)
  73                        zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  74                                          otap_delay);
  75
  76                zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
  77        } else {
  78                zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
  79                                  SD1_DLL_RST);
  80                /* Program ITAP */
  81                if (itap_delay) {
  82                        zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
  83                                          SD1_ITAPCHGWIN);
  84                        zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
  85                                          SD1_ITAPDLYENA);
  86                        zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
  87                                          (itap_delay << 16));
  88                        zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
  89                                          0x0);
  90                }
  91
  92                /* Program OTAP */
  93                if (otap_delay)
  94                        zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  95                                          (otap_delay << 16));
  96
  97                zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
  98        }
  99}
 100