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7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/imx-regs.h>
12#include <dt-bindings/clock/imx6qdl-clock.h>
13
14#include "clk.h"
15
16static int imx6q_check_id(ulong id)
17{
18 if (id < IMX6QDL_CLK_DUMMY || id >= IMX6QDL_CLK_END) {
19 printf("%s: Invalid clk ID #%lu\n", __func__, id);
20 return -EINVAL;
21 }
22
23 return 0;
24}
25
26static ulong imx6q_clk_get_rate(struct clk *clk)
27{
28 struct clk *c;
29 int ret;
30
31 debug("%s(#%lu)\n", __func__, clk->id);
32
33 ret = imx6q_check_id(clk->id);
34 if (ret)
35 return ret;
36
37 ret = clk_get_by_id(clk->id, &c);
38 if (ret)
39 return ret;
40
41 return clk_get_rate(c);
42}
43
44static ulong imx6q_clk_set_rate(struct clk *clk, unsigned long rate)
45{
46 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
47
48 return rate;
49}
50
51static int __imx6q_clk_enable(struct clk *clk, bool enable)
52{
53 struct clk *c;
54 int ret = 0;
55
56 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
57
58 ret = imx6q_check_id(clk->id);
59 if (ret)
60 return ret;
61
62 ret = clk_get_by_id(clk->id, &c);
63 if (ret)
64 return ret;
65
66 if (enable)
67 ret = clk_enable(c);
68 else
69 ret = clk_disable(c);
70
71 return ret;
72}
73
74static int imx6q_clk_disable(struct clk *clk)
75{
76 return __imx6q_clk_enable(clk, 0);
77}
78
79static int imx6q_clk_enable(struct clk *clk)
80{
81 return __imx6q_clk_enable(clk, 1);
82}
83
84static struct clk_ops imx6q_clk_ops = {
85 .set_rate = imx6q_clk_set_rate,
86 .get_rate = imx6q_clk_get_rate,
87 .enable = imx6q_clk_enable,
88 .disable = imx6q_clk_disable,
89};
90
91static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
92static const char *const periph_sels[] = { "periph_pre", "periph_clk2", };
93static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
94 "pll2_pfd0_352m", "pll2_198m", };
95
96static int imx6q_clk_probe(struct udevice *dev)
97{
98 void *base;
99
100
101 base = (void *)ANATOP_BASE_ADDR;
102
103 clk_dm(IMX6QDL_CLK_PLL2,
104 imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
105 base + 0x30, 0x1));
106 clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
107 imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
108 base + 0x10, 0x3));
109 clk_dm(IMX6QDL_CLK_PLL3_60M,
110 imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
111 clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
112 imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
113 clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
114 imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
115
116
117 base = dev_read_addr_ptr(dev);
118 if (base == (void *)FDT_ADDR_T_NONE)
119 return -EINVAL;
120
121 clk_dm(IMX6QDL_CLK_USDHC1_SEL,
122 imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
123 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
124 clk_dm(IMX6QDL_CLK_USDHC2_SEL,
125 imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
126 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
127 clk_dm(IMX6QDL_CLK_USDHC3_SEL,
128 imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
129 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
130 clk_dm(IMX6QDL_CLK_USDHC4_SEL,
131 imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
132 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
133
134 clk_dm(IMX6QDL_CLK_USDHC1_PODF,
135 imx_clk_divider("usdhc1_podf", "usdhc1_sel",
136 base + 0x24, 11, 3));
137 clk_dm(IMX6QDL_CLK_USDHC2_PODF,
138 imx_clk_divider("usdhc2_podf", "usdhc2_sel",
139 base + 0x24, 16, 3));
140 clk_dm(IMX6QDL_CLK_USDHC3_PODF,
141 imx_clk_divider("usdhc3_podf", "usdhc3_sel",
142 base + 0x24, 19, 3));
143 clk_dm(IMX6QDL_CLK_USDHC4_PODF,
144 imx_clk_divider("usdhc4_podf", "usdhc4_sel",
145 base + 0x24, 22, 3));
146
147 clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
148 imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
149
150 clk_dm(IMX6QDL_CLK_ECSPI1,
151 imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
152 clk_dm(IMX6QDL_CLK_ECSPI2,
153 imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
154 clk_dm(IMX6QDL_CLK_ECSPI3,
155 imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
156 clk_dm(IMX6QDL_CLK_ECSPI4,
157 imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
158 clk_dm(IMX6QDL_CLK_USDHC1,
159 imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
160 clk_dm(IMX6QDL_CLK_USDHC2,
161 imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
162 clk_dm(IMX6QDL_CLK_USDHC3,
163 imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
164 clk_dm(IMX6QDL_CLK_USDHC4,
165 imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
166
167 clk_dm(IMX6QDL_CLK_PERIPH_PRE,
168 imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels,
169 ARRAY_SIZE(periph_pre_sels)));
170 clk_dm(IMX6QDL_CLK_PERIPH,
171 imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48,
172 5, periph_sels, ARRAY_SIZE(periph_sels)));
173 clk_dm(IMX6QDL_CLK_AHB,
174 imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3,
175 base + 0x48, 1));
176 clk_dm(IMX6QDL_CLK_IPG,
177 imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2));
178 clk_dm(IMX6QDL_CLK_IPG_PER,
179 imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6));
180 clk_dm(IMX6QDL_CLK_I2C1,
181 imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6));
182 clk_dm(IMX6QDL_CLK_I2C2,
183 imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
184
185 return 0;
186}
187
188static const struct udevice_id imx6q_clk_ids[] = {
189 { .compatible = "fsl,imx6q-ccm" },
190 { },
191};
192
193U_BOOT_DRIVER(imx6q_clk) = {
194 .name = "clk_imx6q",
195 .id = UCLASS_CLK,
196 .of_match = imx6q_clk_ids,
197 .ops = &imx6q_clk_ops,
198 .probe = imx6q_clk_probe,
199 .flags = DM_FLAG_PRE_RELOC,
200};
201
