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10#include <common.h>
11#include <env.h>
12#include <malloc.h>
13#include <command.h>
14#include <config.h>
15#include <net.h>
16#include <miiphy.h>
17#include <linux/mii.h>
18
19#undef ET_DEBUG
20#undef MII_DEBUG
21
22
23#define DBUF_LENGTH 1520
24#define PKT_MAXBUF_SIZE 1518
25#define PKT_MINBUF_SIZE 64
26#define PKT_MAXBLR_SIZE 1536
27#define LAST_PKTBUFSRX PKTBUFSRX - 1
28#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
29#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
30#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
31
32
33#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
34 BD_ENET_RX_OV | BD_ENET_RX_TR)
35
36#include <asm/immap.h>
37#include <asm/fsl_mcdmafec.h>
38
39#include "MCD_dma.h"
40
41struct fec_info_dma fec_info[] = {
42#ifdef CONFIG_SYS_FEC0_IOBASE
43 {
44 0,
45 CONFIG_SYS_FEC0_IOBASE,
46 CONFIG_SYS_FEC0_PINMUX,
47 CONFIG_SYS_FEC0_MIIBASE,
48 -1,
49 0,
50 0,
51 0,
52 0,
53 0,
54 0,
55 0,
56 0,
57 0,
58 (struct fec_info_dma *)-1,
59 FEC0_RX_TASK,
60 FEC0_TX_TASK,
61 FEC0_RX_PRIORITY,
62 FEC0_TX_PRIORITY,
63 FEC0_RX_INIT,
64 FEC0_TX_INIT,
65 0,
66 0,
67 },
68#endif
69#ifdef CONFIG_SYS_FEC1_IOBASE
70 {
71 1,
72 CONFIG_SYS_FEC1_IOBASE,
73 CONFIG_SYS_FEC1_PINMUX,
74 CONFIG_SYS_FEC1_MIIBASE,
75 -1,
76 0,
77 0,
78 0,
79#ifdef CONFIG_SYS_DMA_USE_INTSRAM
80 (cbd_t *)DBUF_LENGTH,
81#else
82 0,
83#endif
84 0,
85 0,
86 0,
87 0,
88 0,
89 (struct fec_info_dma *)-1,
90 FEC1_RX_TASK,
91 FEC1_TX_TASK,
92 FEC1_RX_PRIORITY,
93 FEC1_TX_PRIORITY,
94 FEC1_RX_INIT,
95 FEC1_TX_INIT,
96 0,
97 0,
98 }
99#endif
100};
101
102static int fec_send(struct eth_device *dev, void *packet, int length);
103static int fec_recv(struct eth_device *dev);
104static int fec_init(struct eth_device *dev, bd_t * bd);
105static void fec_halt(struct eth_device *dev);
106
107#ifdef ET_DEBUG
108static void dbg_fec_regs(struct eth_device *dev)
109{
110 struct fec_info_dma *info = dev->priv;
111 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
112
113 printf("=====\n");
114 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
115 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
116 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
117 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
118 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
119 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
120 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
121 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
122 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
123 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
124 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
125 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
126 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
127 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
128 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
129 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
130 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
131 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
132 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
133 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
134 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
135 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
136 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
137 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
138 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
139 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
140 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
141 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
142 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
143 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
144 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
145 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
146 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
147 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
148 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
149}
150#endif
151
152static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
153 int dup_spd)
154{
155 if ((dup_spd >> 16) == FULL) {
156
157 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
158 FEC_RCR_PROM | 0x100;
159 fecp->tcr = FEC_TCR_FDEN;
160 } else {
161
162 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
163 FEC_RCR_MII_MODE | FEC_RCR_DRT;
164 fecp->tcr &= ~FEC_TCR_FDEN;
165 }
166
167 if ((dup_spd & 0xFFFF) == _100BASET) {
168#ifdef MII_DEBUG
169 printf("100Mbps\n");
170#endif
171 bd->bi_ethspeed = 100;
172 } else {
173#ifdef MII_DEBUG
174 printf("10Mbps\n");
175#endif
176 bd->bi_ethspeed = 10;
177 }
178}
179
180static int fec_send(struct eth_device *dev, void *packet, int length)
181{
182 struct fec_info_dma *info = dev->priv;
183 cbd_t *pTbd, *pUsedTbd;
184 u16 phyStatus;
185
186 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
187
188
189 while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
190 pUsedTbd = &info->txbd[info->usedTbdIdx];
191 if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
192#ifdef ET_DEBUG
193 printf("Cannot clean TBD %d, in use\n",
194 info->cleanTbdNum);
195#endif
196 return 0;
197 }
198
199
200 if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
201 pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
202 else
203 pUsedTbd->cbd_sc = 0;
204
205
206 info->cleanTbdNum++;
207 info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
208 }
209
210
211 if ((length > 1500) || (length <= 0)) {
212 return -1;
213 }
214
215
216 if (info->cleanTbdNum < 1) {
217 printf("No available TxBDs ...\n");
218 return -1;
219 }
220
221
222 pTbd = &info->txbd[info->txIdx];
223 pTbd->cbd_datlen = length;
224 pTbd->cbd_bufaddr = (u32) packet;
225 pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
226 info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
227
228
229 MCD_continDma(info->txTask);
230
231 info->cleanTbdNum -= 1;
232
233
234 while (pTbd->cbd_sc & BD_ENET_TX_READY) {
235 udelay(10);
236 }
237
238 return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
239}
240
241static int fec_recv(struct eth_device *dev)
242{
243 struct fec_info_dma *info = dev->priv;
244 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
245
246 cbd_t *prbd = &info->rxbd[info->rxIdx];
247 u32 ievent;
248 int frame_length, len = 0;
249
250
251 ievent = fecp->eir;
252 if (ievent != 0) {
253 fecp->eir = ievent;
254
255 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
256 printf("fec_recv: error\n");
257 fec_halt(dev);
258 fec_init(dev, NULL);
259 return 0;
260 }
261
262 if (ievent & FEC_EIR_HBERR) {
263
264 fecp->tcr |= FEC_TCR_GTS;
265 }
266
267 if (ievent & FEC_EIR_GRA) {
268
269 if (fecp->tcr & FEC_TCR_GTS) {
270 printf("fec_recv: tcr_gts\n");
271 fec_halt(dev);
272 fecp->tcr &= ~FEC_TCR_GTS;
273 fec_init(dev, NULL);
274 }
275 }
276 }
277
278 if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
279 if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
280 !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
281 ((prbd->cbd_datlen - 4) > 14)) {
282
283
284 frame_length = prbd->cbd_datlen - 4;
285
286
287 net_process_received_packet((uchar *)prbd->cbd_bufaddr,
288 frame_length);
289 len = frame_length;
290 }
291
292
293 if ((info->rxIdx) == (PKTBUFSRX - 1))
294 prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
295 else
296 prbd->cbd_sc = BD_ENET_RX_EMPTY;
297
298 prbd->cbd_datlen = PKTSIZE_ALIGN;
299
300
301 MCD_continDma(info->rxTask);
302
303
304 info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
305 }
306
307 return len;
308}
309
310static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
311{
312 u8 currByte;
313 int byte;
314 int bit;
315 u32 crc = 0xffffffff;
316
317 for (byte = 0; byte < 6; byte++) {
318 currByte = mac[byte];
319 for (bit = 0; bit < 8; bit++) {
320 if ((currByte & 0x01) ^ (crc & 0x01)) {
321 crc >>= 1;
322 crc = crc ^ 0xedb88320;
323 } else {
324 crc >>= 1;
325 }
326 currByte >>= 1;
327 }
328 }
329
330 crc = crc >> 26;
331
332
333 if (crc >= 32) {
334 fecp->ialr = (1 << (crc - 32));
335 fecp->iaur = 0;
336 } else {
337 fecp->ialr = 0;
338 fecp->iaur = (1 << crc);
339 }
340
341
342 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
343 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
344
345
346 fecp->gaur = 0;
347 fecp->galr = 0;
348}
349
350static int fec_init(struct eth_device *dev, bd_t * bd)
351{
352 struct fec_info_dma *info = dev->priv;
353 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
354 int i;
355 uchar enetaddr[6];
356
357#ifdef ET_DEBUG
358 printf("fec_init: iobase 0x%08x ...\n", info->iobase);
359#endif
360
361 fecpin_setclear(dev, 1);
362
363 fec_halt(dev);
364
365#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
366 defined (CONFIG_SYS_DISCOVER_PHY)
367
368 mii_init();
369
370 set_fec_duplex_speed(fecp, bd, info->dup_spd);
371#else
372#ifndef CONFIG_SYS_DISCOVER_PHY
373 set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
374#endif
375#endif
376
377
378 fecp->eimr = 0;
379
380
381 fecp->eir = 0xffffffff;
382
383
384 if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
385 eth_env_get_enetaddr("ethaddr", enetaddr);
386 else
387 eth_env_get_enetaddr("eth1addr", enetaddr);
388 fec_set_hwaddr(fecp, enetaddr);
389
390
391 fecp->opd = 0x00010020;
392
393
394 info->rxIdx = 0;
395 info->txIdx = 0;
396
397
398
399 for (i = 0; i < PKTBUFSRX; i++) {
400 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
401 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
402 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
403 }
404 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
405
406
407
408 for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
409 info->txbd[i].cbd_sc = 0;
410 info->txbd[i].cbd_datlen = 0;
411 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
412 }
413 info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
414
415 info->usedTbdIdx = 0;
416 info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
417
418
419 fecp->rfcr = 0x0c000000;
420 fecp->rfar = 0x0000030c;
421
422
423 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
424 fecp->tfar = 0x00000080;
425
426 fecp->tfwr = 0x2;
427 fecp->ctcwr = 0x03000000;
428
429
430 MCD_startDma(info->rxTask,
431 (s8 *) info->rxbd,
432 0,
433 (s8 *) (&fecp->rfdr),
434 4,
435 0,
436 4,
437 info->rxInit,
438 info->rxPri,
439 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
440 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
441 );
442
443
444 MCD_startDma(info->txTask,
445 (s8 *) info->txbd,
446 0,
447 (s8 *) (&fecp->tfdr),
448 4,
449 0,
450 4,
451 info->txInit,
452 info->txPri,
453 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
454 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
455 );
456
457
458 fecp->ecr |= FEC_ECR_ETHER_EN;
459
460 return 1;
461}
462
463static void fec_halt(struct eth_device *dev)
464{
465 struct fec_info_dma *info = dev->priv;
466 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
467 int counter = 0xffff;
468
469
470 fecp->tcr |= FEC_TCR_GTS;
471
472
473 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
474
475
476 MCD_killDma(info->txTask);
477 MCD_killDma(info->rxTask);
478
479
480 fecp->ecr &= ~FEC_ECR_ETHER_EN;
481
482
483 fecp->rfsr &= FIFO_ERRSTAT;
484 fecp->tfsr &= FIFO_ERRSTAT;
485
486 fecp->frst = 0x01000000;
487
488
489 fecp->ecr |= FEC_ECR_RESET;
490
491
492 udelay(10000);
493
494#ifdef ET_DEBUG
495 printf("Ethernet task stopped\n");
496#endif
497}
498
499int mcdmafec_initialize(bd_t * bis)
500{
501 struct eth_device *dev;
502 int i;
503#ifdef CONFIG_SYS_DMA_USE_INTSRAM
504 u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
505#endif
506
507 for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
508
509 dev =
510 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
511 sizeof *dev);
512 if (dev == NULL)
513 hang();
514
515 memset(dev, 0, sizeof(*dev));
516
517 sprintf(dev->name, "FEC%d", fec_info[i].index);
518
519 dev->priv = &fec_info[i];
520 dev->init = fec_init;
521 dev->halt = fec_halt;
522 dev->send = fec_send;
523 dev->recv = fec_recv;
524
525
526#ifdef CONFIG_SYS_DMA_USE_INTSRAM
527 fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
528 tmp = (u32)fec_info[i].rxbd;
529 fec_info[i].txbd =
530 (cbd_t *)((u32)fec_info[i].txbd + tmp +
531 (PKTBUFSRX * sizeof(cbd_t)));
532 tmp = (u32)fec_info[i].txbd;
533 fec_info[i].txbuf =
534 (char *)((u32)fec_info[i].txbuf + tmp +
535 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
536 tmp = (u32)fec_info[i].txbuf;
537#else
538 fec_info[i].rxbd =
539 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
540 (PKTBUFSRX * sizeof(cbd_t)));
541 fec_info[i].txbd =
542 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
543 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
544 fec_info[i].txbuf =
545 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
546#endif
547
548#ifdef ET_DEBUG
549 printf("rxbd %x txbd %x\n",
550 (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
551#endif
552
553 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
554
555 eth_register(dev);
556
557#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
558 int retval;
559 struct mii_dev *mdiodev = mdio_alloc();
560 if (!mdiodev)
561 return -ENOMEM;
562 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
563 mdiodev->read = mcffec_miiphy_read;
564 mdiodev->write = mcffec_miiphy_write;
565
566 retval = mdio_register(mdiodev);
567 if (retval < 0)
568 return retval;
569#endif
570
571 if (i > 0)
572 fec_info[i - 1].next = &fec_info[i];
573 }
574 fec_info[i - 1].next = &fec_info[0];
575
576
577 bis->bi_ethspeed = 10;
578
579 return 0;
580}
581