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12#define DRV_NAME "sh-pfc"
13
14#include <common.h>
15#include <dm.h>
16#include <errno.h>
17#include <dm/pinctrl.h>
18#include <linux/io.h>
19#include <linux/sizes.h>
20
21#include "sh_pfc.h"
22
23enum sh_pfc_model {
24 SH_PFC_R8A7790 = 0,
25 SH_PFC_R8A7791,
26 SH_PFC_R8A7792,
27 SH_PFC_R8A7793,
28 SH_PFC_R8A7794,
29 SH_PFC_R8A7795,
30 SH_PFC_R8A7796,
31 SH_PFC_R8A77965,
32 SH_PFC_R8A77970,
33 SH_PFC_R8A77980,
34 SH_PFC_R8A77990,
35 SH_PFC_R8A77995,
36};
37
38struct sh_pfc_pin_config {
39 u32 type;
40};
41
42struct sh_pfc_pinctrl {
43 struct sh_pfc *pfc;
44
45 struct sh_pfc_pin_config *configs;
46
47 const char *func_prop_name;
48 const char *groups_prop_name;
49 const char *pins_prop_name;
50};
51
52struct sh_pfc_pin_range {
53 u16 start;
54 u16 end;
55};
56
57struct sh_pfc_pinctrl_priv {
58 struct sh_pfc pfc;
59 struct sh_pfc_pinctrl pmx;
60};
61
62int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
63{
64 unsigned int offset;
65 unsigned int i;
66
67 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
68 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
69
70 if (pin <= range->end)
71 return pin >= range->start
72 ? offset + pin - range->start : -1;
73
74 offset += range->end - range->start + 1;
75 }
76
77 return -EINVAL;
78}
79
80static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
81{
82 if (enum_id < r->begin)
83 return 0;
84
85 if (enum_id > r->end)
86 return 0;
87
88 return 1;
89}
90
91u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
92{
93 switch (reg_width) {
94 case 8:
95 return readb(mapped_reg);
96 case 16:
97 return readw(mapped_reg);
98 case 32:
99 return readl(mapped_reg);
100 }
101
102 BUG();
103 return 0;
104}
105
106void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
107 u32 data)
108{
109 switch (reg_width) {
110 case 8:
111 writeb(data, mapped_reg);
112 return;
113 case 16:
114 writew(data, mapped_reg);
115 return;
116 case 32:
117 writel(data, mapped_reg);
118 return;
119 }
120
121 BUG();
122}
123
124u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
125{
126 return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
127}
128
129void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
130{
131 void __iomem *unlock_reg =
132 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
133
134 if (pfc->info->unlock_reg)
135 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
136
137 sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
138}
139
140static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
141 const struct pinmux_cfg_reg *crp,
142 unsigned int in_pos,
143 void __iomem **mapped_regp, u32 *maskp,
144 unsigned int *posp)
145{
146 unsigned int k;
147
148 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
149
150 if (crp->field_width) {
151 *maskp = (1 << crp->field_width) - 1;
152 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
153 } else {
154 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
155 *posp = crp->reg_width;
156 for (k = 0; k <= in_pos; k++)
157 *posp -= crp->var_field_width[k];
158 }
159}
160
161static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
162 const struct pinmux_cfg_reg *crp,
163 unsigned int field, u32 value)
164{
165 void __iomem *mapped_reg;
166 void __iomem *unlock_reg =
167 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
168 unsigned int pos;
169 u32 mask, data;
170
171 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
172
173 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
174 "r_width = %u, f_width = %u\n",
175 crp->reg, value, field, crp->reg_width, crp->field_width);
176
177 mask = ~(mask << pos);
178 value = value << pos;
179
180 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
181 data &= mask;
182 data |= value;
183
184 if (pfc->info->unlock_reg)
185 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
186
187 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
188}
189
190static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
191 const struct pinmux_cfg_reg **crp,
192 unsigned int *fieldp, u32 *valuep)
193{
194 unsigned int k = 0;
195
196 while (1) {
197 const struct pinmux_cfg_reg *config_reg =
198 pfc->info->cfg_regs + k;
199 unsigned int r_width = config_reg->reg_width;
200 unsigned int f_width = config_reg->field_width;
201 unsigned int curr_width;
202 unsigned int bit_pos;
203 unsigned int pos = 0;
204 unsigned int m = 0;
205
206 if (!r_width)
207 break;
208
209 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
210 u32 ncomb;
211 u32 n;
212
213 if (f_width)
214 curr_width = f_width;
215 else
216 curr_width = config_reg->var_field_width[m];
217
218 ncomb = 1 << curr_width;
219 for (n = 0; n < ncomb; n++) {
220 if (config_reg->enum_ids[pos + n] == enum_id) {
221 *crp = config_reg;
222 *fieldp = m;
223 *valuep = n;
224 return 0;
225 }
226 }
227 pos += ncomb;
228 m++;
229 }
230 k++;
231 }
232
233 return -EINVAL;
234}
235
236static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
237 u16 *enum_idp)
238{
239 const u16 *data = pfc->info->pinmux_data;
240 unsigned int k;
241
242 if (pos) {
243 *enum_idp = data[pos + 1];
244 return pos + 1;
245 }
246
247 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
248 if (data[k] == mark) {
249 *enum_idp = data[k + 1];
250 return k + 1;
251 }
252 }
253
254 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
255 mark);
256 return -EINVAL;
257}
258
259int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
260{
261 const struct pinmux_range *range;
262 int pos = 0;
263
264 switch (pinmux_type) {
265 case PINMUX_TYPE_GPIO:
266 case PINMUX_TYPE_FUNCTION:
267 range = NULL;
268 break;
269
270 case PINMUX_TYPE_OUTPUT:
271 range = &pfc->info->output;
272 break;
273
274 case PINMUX_TYPE_INPUT:
275 range = &pfc->info->input;
276 break;
277
278 default:
279 return -EINVAL;
280 }
281
282
283 while (1) {
284 const struct pinmux_cfg_reg *cr;
285 unsigned int field;
286 u16 enum_id;
287 u32 value;
288 int in_range;
289 int ret;
290
291 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
292 if (pos < 0)
293 return pos;
294
295 if (!enum_id)
296 break;
297
298
299
300
301
302 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
303 if (!in_range) {
304 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
305
306
307
308 in_range = 1;
309 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
310
311
312
313 in_range = sh_pfc_enum_in_range(enum_id, range);
314
315
316
317
318
319
320 if (in_range && enum_id == range->force)
321 continue;
322 }
323
324 }
325
326 if (!in_range)
327 continue;
328
329 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
330 if (ret < 0)
331 return ret;
332
333 sh_pfc_write_config_reg(pfc, cr, field, value);
334 }
335
336 return 0;
337}
338
339const struct pinmux_bias_reg *
340sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
341 unsigned int *bit)
342{
343 unsigned int i, j;
344
345 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
346 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
347 if (pfc->info->bias_regs[i].pins[j] == pin) {
348 *bit = j;
349 return &pfc->info->bias_regs[i];
350 }
351 }
352 }
353
354 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
355
356 return NULL;
357}
358
359static int sh_pfc_init_ranges(struct sh_pfc *pfc)
360{
361 struct sh_pfc_pin_range *range;
362 unsigned int nr_ranges;
363 unsigned int i;
364
365 if (pfc->info->pins[0].pin == (u16)-1) {
366
367
368
369
370 pfc->nr_ranges = 1;
371 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
372 if (pfc->ranges == NULL)
373 return -ENOMEM;
374
375 pfc->ranges->start = 0;
376 pfc->ranges->end = pfc->info->nr_pins - 1;
377 pfc->nr_gpio_pins = pfc->info->nr_pins;
378
379 return 0;
380 }
381
382
383
384
385
386 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
387 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
388 nr_ranges++;
389 }
390
391 pfc->nr_ranges = nr_ranges;
392 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
393 if (pfc->ranges == NULL)
394 return -ENOMEM;
395
396 range = pfc->ranges;
397 range->start = pfc->info->pins[0].pin;
398
399 for (i = 1; i < pfc->info->nr_pins; ++i) {
400 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
401 continue;
402
403 range->end = pfc->info->pins[i-1].pin;
404 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
405 pfc->nr_gpio_pins = range->end + 1;
406
407 range++;
408 range->start = pfc->info->pins[i].pin;
409 }
410
411 range->end = pfc->info->pins[i-1].pin;
412 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
413 pfc->nr_gpio_pins = range->end + 1;
414
415 return 0;
416}
417
418static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
419{
420 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
421
422 return priv->pfc.info->nr_pins;
423}
424
425static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
426 unsigned selector)
427{
428 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
429
430 return priv->pfc.info->pins[selector].name;
431}
432
433static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
434{
435 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
436
437 return priv->pfc.info->nr_groups;
438}
439
440static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
441 unsigned selector)
442{
443 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
444
445 return priv->pfc.info->groups[selector].name;
446}
447
448static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
449{
450 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
451
452 return priv->pfc.info->nr_functions;
453}
454
455static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
456 unsigned selector)
457{
458 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
459
460 return priv->pfc.info->functions[selector].name;
461}
462
463static int sh_pfc_gpio_request_enable(struct udevice *dev,
464 unsigned pin_selector)
465{
466 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
467 struct sh_pfc_pinctrl *pmx = &priv->pmx;
468 struct sh_pfc *pfc = &priv->pfc;
469 struct sh_pfc_pin_config *cfg;
470 const struct sh_pfc_pin *pin = NULL;
471 int i, ret, idx;
472
473 for (i = 0; i < pfc->info->nr_pins; i++) {
474 if (priv->pfc.info->pins[i].pin != pin_selector)
475 continue;
476
477 pin = &priv->pfc.info->pins[i];
478 break;
479 }
480
481 if (!pin)
482 return -EINVAL;
483
484 idx = sh_pfc_get_pin_index(pfc, pin->pin);
485 cfg = &pmx->configs[idx];
486
487 if (cfg->type != PINMUX_TYPE_NONE)
488 return -EBUSY;
489
490 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
491 if (ret)
492 return ret;
493
494 cfg->type = PINMUX_TYPE_GPIO;
495
496 return 0;
497}
498
499static int sh_pfc_gpio_disable_free(struct udevice *dev,
500 unsigned pin_selector)
501{
502 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
503 struct sh_pfc_pinctrl *pmx = &priv->pmx;
504 struct sh_pfc *pfc = &priv->pfc;
505 struct sh_pfc_pin_config *cfg;
506 const struct sh_pfc_pin *pin = NULL;
507 int i, idx;
508
509 for (i = 0; i < pfc->info->nr_pins; i++) {
510 if (priv->pfc.info->pins[i].pin != pin_selector)
511 continue;
512
513 pin = &priv->pfc.info->pins[i];
514 break;
515 }
516
517 if (!pin)
518 return -EINVAL;
519
520 idx = sh_pfc_get_pin_index(pfc, pin->pin);
521 cfg = &pmx->configs[idx];
522
523 cfg->type = PINMUX_TYPE_NONE;
524
525 return 0;
526}
527
528static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
529 unsigned func_selector)
530{
531 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
532 struct sh_pfc_pinctrl *pmx = &priv->pmx;
533 struct sh_pfc *pfc = &priv->pfc;
534 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
535 int idx = sh_pfc_get_pin_index(pfc, pin->pin);
536 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
537
538 if (cfg->type != PINMUX_TYPE_NONE)
539 return -EBUSY;
540
541 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
542}
543
544static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
545 unsigned func_selector)
546{
547 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
548 struct sh_pfc_pinctrl *pmx = &priv->pmx;
549 struct sh_pfc *pfc = &priv->pfc;
550 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
551 unsigned int i;
552 int ret = 0;
553
554 for (i = 0; i < grp->nr_pins; ++i) {
555 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
556 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
557
558 if (cfg->type != PINMUX_TYPE_NONE) {
559 ret = -EBUSY;
560 goto done;
561 }
562 }
563
564 for (i = 0; i < grp->nr_pins; ++i) {
565 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
566 if (ret < 0)
567 break;
568 }
569
570done:
571 return ret;
572}
573#if CONFIG_IS_ENABLED(PINCONF)
574static const struct pinconf_param sh_pfc_pinconf_params[] = {
575 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
576 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
577 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
578 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
579 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
580};
581
582static void __iomem *
583sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
584 unsigned int *offset, unsigned int *size)
585{
586 const struct pinmux_drive_reg_field *field;
587 const struct pinmux_drive_reg *reg;
588 unsigned int i;
589
590 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
591 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
592 field = ®->fields[i];
593
594 if (field->size && field->pin == pin) {
595 *offset = field->offset;
596 *size = field->size;
597
598 return (void __iomem *)(uintptr_t)reg->reg;
599 }
600 }
601 }
602
603 return NULL;
604}
605
606static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
607 unsigned int pin, u16 strength)
608{
609 unsigned int offset;
610 unsigned int size;
611 unsigned int step;
612 void __iomem *reg;
613 void __iomem *unlock_reg =
614 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
615 u32 val;
616
617 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
618 if (!reg)
619 return -EINVAL;
620
621 step = size == 2 ? 6 : 3;
622
623 if (strength < step || strength > 24)
624 return -EINVAL;
625
626
627
628
629 strength = strength / step - 1;
630
631 val = sh_pfc_read_raw_reg(reg, 32);
632 val &= ~GENMASK(offset + 4 - 1, offset);
633 val |= strength << offset;
634
635 if (unlock_reg)
636 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
637
638 sh_pfc_write_raw_reg(reg, 32, val);
639
640 return 0;
641}
642
643
644static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
645 unsigned int param)
646{
647 int idx = sh_pfc_get_pin_index(pfc, _pin);
648 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
649
650 switch (param) {
651 case PIN_CONFIG_BIAS_DISABLE:
652 return pin->configs &
653 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
654
655 case PIN_CONFIG_BIAS_PULL_UP:
656 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
657
658 case PIN_CONFIG_BIAS_PULL_DOWN:
659 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
660
661 case PIN_CONFIG_DRIVE_STRENGTH:
662 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
663
664 case PIN_CONFIG_POWER_SOURCE:
665 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
666
667 default:
668 return false;
669 }
670}
671
672static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
673 unsigned int param, unsigned int arg)
674{
675 struct sh_pfc *pfc = pmx->pfc;
676 void __iomem *pocctrl;
677 void __iomem *unlock_reg =
678 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
679 u32 addr, val;
680 int bit, ret;
681
682 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
683 return -ENOTSUPP;
684
685 switch (param) {
686 case PIN_CONFIG_BIAS_PULL_UP:
687 case PIN_CONFIG_BIAS_PULL_DOWN:
688 case PIN_CONFIG_BIAS_DISABLE:
689 if (!pfc->info->ops || !pfc->info->ops->set_bias)
690 return -ENOTSUPP;
691
692 pfc->info->ops->set_bias(pfc, _pin, param);
693
694 break;
695
696 case PIN_CONFIG_DRIVE_STRENGTH:
697 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
698 if (ret < 0)
699 return ret;
700
701 break;
702
703 case PIN_CONFIG_POWER_SOURCE:
704 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
705 return -ENOTSUPP;
706
707 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
708 if (bit < 0) {
709 printf("invalid pin %#x", _pin);
710 return bit;
711 }
712
713 if (arg != 1800 && arg != 3300)
714 return -EINVAL;
715
716 pocctrl = (void __iomem *)(uintptr_t)addr;
717
718 val = sh_pfc_read_raw_reg(pocctrl, 32);
719 if (arg == 3300)
720 val |= BIT(bit);
721 else
722 val &= ~BIT(bit);
723
724 if (unlock_reg)
725 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
726
727 sh_pfc_write_raw_reg(pocctrl, 32, val);
728
729 break;
730
731 default:
732 return -ENOTSUPP;
733 }
734
735 return 0;
736}
737
738static int sh_pfc_pinconf_pin_set(struct udevice *dev,
739 unsigned int pin_selector,
740 unsigned int param, unsigned int arg)
741{
742 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
743 struct sh_pfc_pinctrl *pmx = &priv->pmx;
744 struct sh_pfc *pfc = &priv->pfc;
745 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
746
747 sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
748
749 return 0;
750}
751
752static int sh_pfc_pinconf_group_set(struct udevice *dev,
753 unsigned int group_selector,
754 unsigned int param, unsigned int arg)
755{
756 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
757 struct sh_pfc_pinctrl *pmx = &priv->pmx;
758 struct sh_pfc *pfc = &priv->pfc;
759 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
760 unsigned int i;
761
762 for (i = 0; i < grp->nr_pins; i++)
763 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
764
765 return 0;
766}
767#endif
768
769static struct pinctrl_ops sh_pfc_pinctrl_ops = {
770 .get_pins_count = sh_pfc_pinctrl_get_pins_count,
771 .get_pin_name = sh_pfc_pinctrl_get_pin_name,
772 .get_groups_count = sh_pfc_pinctrl_get_groups_count,
773 .get_group_name = sh_pfc_pinctrl_get_group_name,
774 .get_functions_count = sh_pfc_pinctrl_get_functions_count,
775 .get_function_name = sh_pfc_pinctrl_get_function_name,
776
777#if CONFIG_IS_ENABLED(PINCONF)
778 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
779 .pinconf_params = sh_pfc_pinconf_params,
780 .pinconf_set = sh_pfc_pinconf_pin_set,
781 .pinconf_group_set = sh_pfc_pinconf_group_set,
782#endif
783 .pinmux_set = sh_pfc_pinctrl_pin_set,
784 .pinmux_group_set = sh_pfc_pinctrl_group_set,
785 .set_state = pinctrl_generic_set_state,
786
787 .gpio_request_enable = sh_pfc_gpio_request_enable,
788 .gpio_disable_free = sh_pfc_gpio_disable_free,
789};
790
791static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
792{
793 unsigned int i;
794
795
796 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
797 GFP_KERNEL);
798 if (unlikely(!pmx->configs))
799 return -ENOMEM;
800
801 for (i = 0; i < pfc->info->nr_pins; ++i) {
802 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
803 cfg->type = PINMUX_TYPE_NONE;
804 }
805
806 return 0;
807}
808
809
810static int sh_pfc_pinctrl_probe(struct udevice *dev)
811{
812 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
813 enum sh_pfc_model model = dev_get_driver_data(dev);
814 fdt_addr_t base;
815
816 base = devfdt_get_addr(dev);
817 if (base == FDT_ADDR_T_NONE)
818 return -EINVAL;
819
820 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
821 if (!priv->pfc.regs)
822 return -ENOMEM;
823
824#ifdef CONFIG_PINCTRL_PFC_R8A7790
825 if (model == SH_PFC_R8A7790)
826 priv->pfc.info = &r8a7790_pinmux_info;
827#endif
828#ifdef CONFIG_PINCTRL_PFC_R8A7791
829 if (model == SH_PFC_R8A7791)
830 priv->pfc.info = &r8a7791_pinmux_info;
831#endif
832#ifdef CONFIG_PINCTRL_PFC_R8A7792
833 if (model == SH_PFC_R8A7792)
834 priv->pfc.info = &r8a7792_pinmux_info;
835#endif
836#ifdef CONFIG_PINCTRL_PFC_R8A7793
837 if (model == SH_PFC_R8A7793)
838 priv->pfc.info = &r8a7793_pinmux_info;
839#endif
840#ifdef CONFIG_PINCTRL_PFC_R8A7794
841 if (model == SH_PFC_R8A7794)
842 priv->pfc.info = &r8a7794_pinmux_info;
843#endif
844#ifdef CONFIG_PINCTRL_PFC_R8A7795
845 if (model == SH_PFC_R8A7795)
846 priv->pfc.info = &r8a7795_pinmux_info;
847#endif
848#ifdef CONFIG_PINCTRL_PFC_R8A7796
849 if (model == SH_PFC_R8A7796)
850 priv->pfc.info = &r8a7796_pinmux_info;
851#endif
852#ifdef CONFIG_PINCTRL_PFC_R8A77965
853 if (model == SH_PFC_R8A77965)
854 priv->pfc.info = &r8a77965_pinmux_info;
855#endif
856#ifdef CONFIG_PINCTRL_PFC_R8A77970
857 if (model == SH_PFC_R8A77970)
858 priv->pfc.info = &r8a77970_pinmux_info;
859#endif
860#ifdef CONFIG_PINCTRL_PFC_R8A77980
861 if (model == SH_PFC_R8A77980)
862 priv->pfc.info = &r8a77980_pinmux_info;
863#endif
864#ifdef CONFIG_PINCTRL_PFC_R8A77990
865 if (model == SH_PFC_R8A77990)
866 priv->pfc.info = &r8a77990_pinmux_info;
867#endif
868#ifdef CONFIG_PINCTRL_PFC_R8A77995
869 if (model == SH_PFC_R8A77995)
870 priv->pfc.info = &r8a77995_pinmux_info;
871#endif
872
873 priv->pmx.pfc = &priv->pfc;
874 sh_pfc_init_ranges(&priv->pfc);
875 sh_pfc_map_pins(&priv->pfc, &priv->pmx);
876
877 return 0;
878}
879
880static const struct udevice_id sh_pfc_pinctrl_ids[] = {
881#ifdef CONFIG_PINCTRL_PFC_R8A7790
882 {
883 .compatible = "renesas,pfc-r8a7790",
884 .data = SH_PFC_R8A7790,
885 },
886#endif
887#ifdef CONFIG_PINCTRL_PFC_R8A7791
888 {
889 .compatible = "renesas,pfc-r8a7791",
890 .data = SH_PFC_R8A7791,
891 },
892#endif
893#ifdef CONFIG_PINCTRL_PFC_R8A7792
894 {
895 .compatible = "renesas,pfc-r8a7792",
896 .data = SH_PFC_R8A7792,
897 },
898#endif
899#ifdef CONFIG_PINCTRL_PFC_R8A7793
900 {
901 .compatible = "renesas,pfc-r8a7793",
902 .data = SH_PFC_R8A7793,
903 },
904#endif
905#ifdef CONFIG_PINCTRL_PFC_R8A7794
906 {
907 .compatible = "renesas,pfc-r8a7794",
908 .data = SH_PFC_R8A7794,
909 },
910#endif
911#ifdef CONFIG_PINCTRL_PFC_R8A7795
912 {
913 .compatible = "renesas,pfc-r8a7795",
914 .data = SH_PFC_R8A7795,
915 },
916#endif
917#ifdef CONFIG_PINCTRL_PFC_R8A7796
918 {
919 .compatible = "renesas,pfc-r8a7796",
920 .data = SH_PFC_R8A7796,
921 },
922#endif
923#ifdef CONFIG_PINCTRL_PFC_R8A77965
924 {
925 .compatible = "renesas,pfc-r8a77965",
926 .data = SH_PFC_R8A77965,
927 },
928#endif
929#ifdef CONFIG_PINCTRL_PFC_R8A77970
930 {
931 .compatible = "renesas,pfc-r8a77970",
932 .data = SH_PFC_R8A77970,
933 },
934#endif
935#ifdef CONFIG_PINCTRL_PFC_R8A77980
936 {
937 .compatible = "renesas,pfc-r8a77980",
938 .data = SH_PFC_R8A77980,
939 },
940#endif
941#ifdef CONFIG_PINCTRL_PFC_R8A77990
942 {
943 .compatible = "renesas,pfc-r8a77990",
944 .data = SH_PFC_R8A77990,
945 },
946#endif
947#ifdef CONFIG_PINCTRL_PFC_R8A77995
948 {
949 .compatible = "renesas,pfc-r8a77995",
950 .data = SH_PFC_R8A77995,
951 },
952#endif
953 { },
954};
955
956U_BOOT_DRIVER(pinctrl_sh_pfc) = {
957 .name = "sh_pfc_pinctrl",
958 .id = UCLASS_PINCTRL,
959 .of_match = sh_pfc_pinctrl_ids,
960 .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
961 .ops = &sh_pfc_pinctrl_ops,
962 .probe = sh_pfc_pinctrl_probe,
963};
964
