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7#ifndef __CADENCE_QSPI_H__
8#define __CADENCE_QSPI_H__
9
10#include <reset.h>
11
12#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
13
14#define CQSPI_NO_DECODER_MAX_CS 4
15#define CQSPI_DECODER_MAX_CS 16
16#define CQSPI_READ_CAPTURE_MAX_DELAY 16
17
18#define CQSPI_REG_POLL_US 1
19#define CQSPI_REG_RETRY 10000
20#define CQSPI_POLL_IDLE_RETRY 3
21
22
23#define CQSPI_INST_TYPE_SINGLE 0
24#define CQSPI_INST_TYPE_DUAL 1
25#define CQSPI_INST_TYPE_QUAD 2
26#define CQSPI_INST_TYPE_OCTAL 3
27
28#define CQSPI_STIG_DATA_LEN_MAX 8
29
30#define CQSPI_DUMMY_CLKS_PER_BYTE 8
31#define CQSPI_DUMMY_BYTES_MAX 4
32
33
34
35
36#define CQSPI_REG_CONFIG 0x00
37#define CQSPI_REG_CONFIG_ENABLE BIT(0)
38#define CQSPI_REG_CONFIG_CLK_POL BIT(1)
39#define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
40#define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3)
41#define CQSPI_REG_CONFIG_DIRECT BIT(7)
42#define CQSPI_REG_CONFIG_DECODE BIT(9)
43#define CQSPI_REG_CONFIG_ENBL_DMA BIT(15)
44#define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
45#define CQSPI_REG_CONFIG_DTR_PROT_EN_MASK BIT(24)
46#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
47#define CQSPI_REG_CONFIG_BAUD_LSB 19
48#define CQSPI_REG_CONFIG_IDLE_LSB 31
49#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
50#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
51
52#define CQSPI_REG_RD_INSTR 0x04
53#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
54#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
55#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
56#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
57#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
58#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
59#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
60#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
61#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
62#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
63
64#define CQSPI_REG_WR_INSTR 0x08
65#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
66#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
67
68#define CQSPI_REG_DELAY 0x0C
69#define CQSPI_REG_DELAY_TSLCH_LSB 0
70#define CQSPI_REG_DELAY_TCHSH_LSB 8
71#define CQSPI_REG_DELAY_TSD2D_LSB 16
72#define CQSPI_REG_DELAY_TSHSL_LSB 24
73#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
74#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
75#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
76#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
77
78#define CQSPI_REG_RD_DATA_CAPTURE 0x10
79#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
80#define CQSPI_REG_READCAPTURE_DQS_ENABLE BIT(8)
81#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
82#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
83
84#define CQSPI_REG_SIZE 0x14
85#define CQSPI_REG_SIZE_ADDRESS_LSB 0
86#define CQSPI_REG_SIZE_PAGE_LSB 4
87#define CQSPI_REG_SIZE_BLOCK_LSB 16
88#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
89#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
90#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
91
92#define CQSPI_REG_SRAMPARTITION 0x18
93#define CQSPI_REG_INDIRECTTRIGGER 0x1C
94
95#define CQSPI_REG_REMAP 0x24
96#define CQSPI_REG_MODE_BIT 0x28
97
98#define CQSPI_REG_SDRAMLEVEL 0x2C
99#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
100#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
101#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
102#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
103
104#define CQSPI_REG_IRQSTATUS 0x40
105#define CQSPI_REG_IRQMASK 0x44
106
107#define CQSPI_REG_INDIRECTRD 0x60
108#define CQSPI_REG_INDIRECTRD_START BIT(0)
109#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
110#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
111#define CQSPI_REG_INDIRECTRD_DONE BIT(5)
112
113#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
114#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
115#define CQSPI_REG_INDIRECTRDBYTES 0x6C
116
117#define CQSPI_REG_CMDCTRL 0x90
118#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
119#define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
120#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
121#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
122#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
123#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
124#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
125#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
126#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
127#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
128#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
129#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
130#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
131#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
132#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
133
134#define CQSPI_REG_INDIRECTWR 0x70
135#define CQSPI_REG_INDIRECTWR_START BIT(0)
136#define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
137#define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
138#define CQSPI_REG_INDIRECTWR_DONE BIT(5)
139
140#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
141#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
142#define CQSPI_REG_INDIRECTWRBYTES 0x7C
143
144#define CQSPI_REG_CMDADDRESS 0x94
145#define CQSPI_REG_CMDREADDATALOWER 0xA0
146#define CQSPI_REG_CMDREADDATAUPPER 0xA4
147#define CQSPI_REG_CMDWRITEDATALOWER 0xA8
148#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
149
150#define CQSPI_REG_PHY_CONFIG 0xB4
151#define CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK 0x40000000
152
153#define CQSPI_DMA_DST_ADDR_REG 0x1800
154#define CQSPI_DMA_DST_SIZE_REG 0x1804
155#define CQSPI_DMA_DST_STS_REG 0x1808
156#define CQSPI_DMA_DST_CTRL_REG 0x180C
157#define CQSPI_DMA_DST_I_STS_REG 0x1814
158#define CQSPI_DMA_DST_I_ENBL_REG 0x1818
159#define CQSPI_DMA_DST_I_DISBL_REG 0x181C
160#define CQSPI_DMA_DST_CTRL2_REG 0x1824
161#define CQSPI_DMA_DST_ADDR_MSB_REG 0x1828
162
163#define CQSPI_DMA_SRC_RD_ADDR_REG 0x1000
164
165#define CQSPI_REG_DMA_PERIPH_CFG 0x20
166#define CQSPI_REG_INDIR_TRIG_ADDR_RANGE 0x80
167#define CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE 6
168#define CQSPI_DFLT_DMA_PERIPH_CFG 0x602
169#define CQSPI_DFLT_DST_CTRL_REG_VAL 0xF43FFA00
170
171#define CQSPI_DMA_DST_I_STS_DONE BIT(1)
172#define CQSPI_DMA_TIMEOUT 10000000
173
174#define CQSPI_REG_IS_IDLE(base) \
175 ((readl(base + CQSPI_REG_CONFIG) >> \
176 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
177
178#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
179 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
180 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
181
182#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
183 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
184 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
185
186struct cadence_spi_platdata {
187 unsigned int ref_clk_hz;
188 unsigned int max_hz;
189 void *regbase;
190 void *ahbbase;
191 bool is_decoded_cs;
192 u32 fifo_depth;
193 u32 fifo_width;
194 u32 trigger_address;
195
196
197 u32 page_size;
198 u32 block_size;
199 u32 tshsl_ns;
200 u32 tsd2d_ns;
201 u32 tchsh_ns;
202 u32 tslch_ns;
203 bool is_dma;
204 bool stg_pgm;
205};
206
207struct cadence_spi_priv {
208 void *regbase;
209 void *ahbbase;
210 size_t cmd_len;
211 u8 cmd_buf[32];
212 size_t data_len;
213
214 int qspi_is_init;
215 unsigned int qspi_calibrated_hz;
216 unsigned int qspi_calibrated_cs;
217 unsigned int previous_hz;
218
219 struct reset_ctl_bulk resets;
220};
221
222
223void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
224void cadence_qspi_apb_controller_enable(void *reg_base_addr);
225void cadence_qspi_apb_controller_disable(void *reg_base_addr);
226
227int cadence_qspi_apb_command_read(void *reg_base_addr,
228 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
229int cadence_qspi_apb_command_write(struct udevice *dev,
230 unsigned int cmdlen, const u8 *cmdbuf,
231 unsigned int txlen, const u8 *txbuf);
232
233int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
234 unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
235int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
236 unsigned int rxlen, u8 *rxbuf);
237int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
238 unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf);
239int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
240 unsigned int txlen, const u8 *txbuf);
241
242void cadence_qspi_apb_chipselect(void *reg_base,
243 unsigned int chip_select, unsigned int decoder_enable);
244void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
245void cadence_qspi_apb_config_baudrate_div(void *reg_base,
246 unsigned int ref_clk_hz, unsigned int sclk_hz);
247void cadence_qspi_apb_delay(void *reg_base,
248 unsigned int ref_clk, unsigned int sclk_hz,
249 unsigned int tshsl_ns, unsigned int tsd2d_ns,
250 unsigned int tchsh_ns, unsigned int tslch_ns);
251void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
252void cadence_qspi_apb_readdata_capture(void *reg_base,
253 unsigned int bypass, unsigned int delay);
254int cadence_qspi_apb_dma_read(struct cadence_spi_platdata *plat,
255 unsigned int n_rx, u8 *rxbuf);
256int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg);
257int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_platdata *plat);
258int cadence_spi_versal_flash_reset(struct udevice *dev);
259
260#endif
261
