LXR uboot/drivers/spi/zynq

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2013 Xilinx, Inc.
   4 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
   5 *
   6 * Xilinx Zynq PS SPI controller driver (master mode only)
   7 */
   8
   9#include <common.h>
  10#include <dm.h>
  11#include <malloc.h>
  12#include <spi.h>
  13#include <time.h>
  14#include <clk.h>
  15#include <asm/io.h>
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
  20#define ZYNQ_SPI_CR_MSA_MASK            BIT(15) /* Manual start enb */
  21#define ZYNQ_SPI_CR_MCS_MASK            BIT(14) /* Manual chip select */
  22#define ZYNQ_SPI_CR_CS_MASK             GENMASK(13, 10) /* Chip select */
  23#define ZYNQ_SPI_CR_BAUD_MASK           GENMASK(5, 3)   /* Baud rate div */
  24#define ZYNQ_SPI_CR_CPHA_MASK           BIT(2)  /* Clock phase */
  25#define ZYNQ_SPI_CR_CPOL_MASK           BIT(1)  /* Clock polarity */
  26#define ZYNQ_SPI_CR_MSTREN_MASK         BIT(0)  /* Mode select */
  27#define ZYNQ_SPI_IXR_RXNEMPTY_MASK      BIT(4)  /* RX_FIFO_not_empty */
  28#define ZYNQ_SPI_IXR_TXOW_MASK          BIT(2)  /* TX_FIFO_not_full */
  29#define ZYNQ_SPI_IXR_ALL_MASK           GENMASK(6, 0)   /* All IXR bits */
  30#define ZYNQ_SPI_ENR_SPI_EN_MASK        BIT(0)  /* SPI Enable */
  31
  32#define ZYNQ_SPI_CR_BAUD_MAX            8       /* Baud rate divisor max val */
  33#define ZYNQ_SPI_CR_BAUD_SHIFT          3       /* Baud rate divisor shift */
  34#define ZYNQ_SPI_CR_SS_SHIFT            10      /* Slave select shift */
  35
  36#define ZYNQ_SPI_FIFO_DEPTH             128
  37#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
  38#define CONFIG_SYS_ZYNQ_SPI_WAIT        (CONFIG_SYS_HZ/100)     /* 10 ms */
  39#endif
  40
  41/* zynq spi register set */
  42struct zynq_spi_regs {
  43        u32 cr;         /* 0x00 */
  44        u32 isr;        /* 0x04 */
  45        u32 ier;        /* 0x08 */
  46        u32 idr;        /* 0x0C */
  47        u32 imr;        /* 0x10 */
  48        u32 enr;        /* 0x14 */
  49        u32 dr;         /* 0x18 */
  50        u32 txdr;       /* 0x1C */
  51        u32 rxdr;       /* 0x20 */
  52};
  53
  54
  55/* zynq spi platform data */
  56struct zynq_spi_platdata {
  57        struct zynq_spi_regs *regs;
  58        u32 frequency;          /* input frequency */
  59        u32 speed_hz;
  60        uint deactivate_delay_us;       /* Delay to wait after deactivate */
  61        uint activate_delay_us;         /* Delay to wait after activate */
  62};
  63
  64/* zynq spi priv */
  65struct zynq_spi_priv {
  66        struct zynq_spi_regs *regs;
  67        u8 cs;
  68        u8 mode;
  69        ulong last_transaction_us;      /* Time of last transaction end */
  70        u8 fifo_depth;
  71        u32 freq;               /* required frequency */
  72};
  73
  74static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
  75{
  76        struct zynq_spi_platdata *plat = bus->platdata;
  77        const void *blob = gd->fdt_blob;
  78        int node = dev_of_offset(bus);
  79
  80        plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus);
  81
  82        plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  83                                        "spi-deactivate-delay", 0);
  84        plat->activate_delay_us = fdtdec_get_int(blob, node,
  85                                                 "spi-activate-delay", 0);
  86
  87        return 0;
  88}
  89
  90static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
  91{
  92        struct zynq_spi_regs *regs = priv->regs;
  93        u32 confr;
  94
  95        /* Disable SPI */
  96        confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
  97        writel(~confr, &regs->enr);
  98
  99        /* Disable Interrupts */
 100        writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
 101
 102        /* Clear RX FIFO */
 103        while (readl(&regs->isr) &
 104                        ZYNQ_SPI_IXR_RXNEMPTY_MASK)
 105                readl(&regs->rxdr);
 106
 107        /* Clear Interrupts */
 108        writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
 109
 110        /* Manual slave select and Auto start */
 111        confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
 112                ZYNQ_SPI_CR_MSTREN_MASK;
 113        confr &= ~ZYNQ_SPI_CR_MSA_MASK;
 114        writel(confr, &regs->cr);
 115
 116        /* Enable SPI */
 117        writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
 118}
 119
 120static int zynq_spi_probe(struct udevice *bus)
 121{
 122        struct zynq_spi_platdata *plat = dev_get_platdata(bus);
 123        struct zynq_spi_priv *priv = dev_get_priv(bus);
 124        struct clk clk;
 125        unsigned long clock;
 126        int ret;
 127
 128        priv->regs = plat->regs;
 129        priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
 130
 131        ret = clk_get_by_name(bus, "ref_clk", &clk);
 132        if (ret < 0) {
 133                dev_err(dev, "failed to get clock\n");
 134                return ret;
 135        }
 136
 137        clock = clk_get_rate(&clk);
 138        if (IS_ERR_VALUE(clock)) {
 139                dev_err(dev, "failed to get rate\n");
 140                return clock;
 141        }
 142
 143        ret = clk_enable(&clk);
 144        if (ret && ret != -ENOSYS) {
 145                dev_err(dev, "failed to enable clock\n");
 146                return ret;
 147        }
 148
 149        /* init the zynq spi hw */
 150        zynq_spi_init_hw(priv);
 151
 152        plat->frequency = clock;
 153        plat->speed_hz = plat->frequency / 2;
 154
 155        debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
 156
 157        return 0;
 158}
 159
 160static void spi_cs_activate(struct udevice *dev)
 161{
 162        struct udevice *bus = dev->parent;
 163        struct zynq_spi_platdata *plat = bus->platdata;
 164        struct zynq_spi_priv *priv = dev_get_priv(bus);
 165        struct zynq_spi_regs *regs = priv->regs;
 166        u32 cr;
 167
 168        /* If it's too soon to do another transaction, wait */
 169        if (plat->deactivate_delay_us && priv->last_transaction_us) {
 170                ulong delay_us;         /* The delay completed so far */
 171                delay_us = timer_get_us() - priv->last_transaction_us;
 172                if (delay_us < plat->deactivate_delay_us)
 173                        udelay(plat->deactivate_delay_us - delay_us);
 174        }
 175
 176        clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
 177        cr = readl(&regs->cr);
 178        /*
 179         * CS cal logic: CS[13:10]
 180         * xxx0 - cs0
 181         * xx01 - cs1
 182         * x011 - cs2
 183         */
 184        cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
 185        writel(cr, &regs->cr);
 186
 187        if (plat->activate_delay_us)
 188                udelay(plat->activate_delay_us);
 189}
 190
 191static void spi_cs_deactivate(struct udevice *dev)
 192{
 193        struct udevice *bus = dev->parent;
 194        struct zynq_spi_platdata *plat = bus->platdata;
 195        struct zynq_spi_priv *priv = dev_get_priv(bus);
 196        struct zynq_spi_regs *regs = priv->regs;
 197
 198        setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
 199
 200        /* Remember time of this transaction so we can honour the bus delay */
 201        if (plat->deactivate_delay_us)
 202                priv->last_transaction_us = timer_get_us();
 203}
 204
 205static int zynq_spi_claim_bus(struct udevice *dev)
 206{
 207        struct udevice *bus = dev->parent;
 208        struct zynq_spi_priv *priv = dev_get_priv(bus);
 209        struct zynq_spi_regs *regs = priv->regs;
 210
 211        writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
 212
 213        return 0;
 214}
 215
 216static int zynq_spi_release_bus(struct udevice *dev)
 217{
 218        struct udevice *bus = dev->parent;
 219        struct zynq_spi_priv *priv = dev_get_priv(bus);
 220        struct zynq_spi_regs *regs = priv->regs;
 221        u32 confr;
 222
 223        confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
 224        writel(~confr, &regs->enr);
 225
 226        return 0;
 227}
 228
 229static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
 230                            const void *dout, void *din, unsigned long flags)
 231{
 232        struct udevice *bus = dev->parent;
 233        struct zynq_spi_priv *priv = dev_get_priv(bus);
 234        struct zynq_spi_regs *regs = priv->regs;
 235        struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 236        u32 len = bitlen / 8;
 237        u32 tx_len = len, rx_len = len, tx_tvl;
 238        const u8 *tx_buf = dout;
 239        u8 *rx_buf = din, buf;
 240        u32 ts, status;
 241
 242        debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
 243              bus->seq, slave_plat->cs, bitlen, len, flags);
 244
 245        if (bitlen % 8) {
 246                debug("spi_xfer: Non byte aligned SPI transfer\n");
 247                return -1;
 248        }
 249
 250        priv->cs = slave_plat->cs;
 251        if (flags & SPI_XFER_BEGIN)
 252                spi_cs_activate(dev);
 253
 254        while (rx_len > 0) {
 255                /* Write the data into TX FIFO - tx threshold is fifo_depth */
 256                tx_tvl = 0;
 257                while ((tx_tvl < priv->fifo_depth) && tx_len) {
 258                        if (tx_buf)
 259                                buf = *tx_buf++;
 260                        else
 261                                buf = 0;
 262                        writel(buf, &regs->txdr);
 263                        tx_len--;
 264                        tx_tvl++;
 265                }
 266
 267                /* Check TX FIFO completion */
 268                ts = get_timer(0);
 269                status = readl(&regs->isr);
 270                while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
 271                        if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
 272                                printf("spi_xfer: Timeout! TX FIFO not full\n");
 273                                return -1;
 274                        }
 275                        status = readl(&regs->isr);
 276                }
 277
 278                /* Read the data from RX FIFO */
 279                status = readl(&regs->isr);
 280                while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
 281                        buf = readl(&regs->rxdr);
 282                        if (rx_buf)
 283                                *rx_buf++ = buf;
 284                        status = readl(&regs->isr);
 285                        rx_len--;
 286                }
 287        }
 288
 289        if (flags & SPI_XFER_END)
 290                spi_cs_deactivate(dev);
 291
 292        return 0;
 293}
 294
 295static int zynq_spi_set_speed(struct udevice *bus, uint speed)
 296{
 297        struct zynq_spi_platdata *plat = bus->platdata;
 298        struct zynq_spi_priv *priv = dev_get_priv(bus);
 299        struct zynq_spi_regs *regs = priv->regs;
 300        uint32_t confr;
 301        u8 baud_rate_val = 0;
 302
 303        if (speed > plat->frequency)
 304                speed = plat->frequency;
 305
 306        /* Set the clock frequency */
 307        confr = readl(&regs->cr);
 308        if (speed == 0) {
 309                /* Set baudrate x8, if the freq is 0 */
 310                baud_rate_val = 0x2;
 311        } else if (plat->speed_hz != speed) {
 312                while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
 313                                ((plat->frequency /
 314                                (2 << baud_rate_val)) > speed))
 315                        baud_rate_val++;
 316                plat->speed_hz = speed / (2 << baud_rate_val);
 317        }
 318        confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
 319        confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
 320
 321        writel(confr, &regs->cr);
 322        priv->freq = speed;
 323
 324        debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
 325              priv->regs, priv->freq);
 326
 327        return 0;
 328}
 329
 330static int zynq_spi_set_mode(struct udevice *bus, uint mode)
 331{
 332        struct zynq_spi_priv *priv = dev_get_priv(bus);
 333        struct zynq_spi_regs *regs = priv->regs;
 334        uint32_t confr;
 335
 336        /* Set the SPI Clock phase and polarities */
 337        confr = readl(&regs->cr);
 338        confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
 339
 340        if (mode & SPI_CPHA)
 341                confr |= ZYNQ_SPI_CR_CPHA_MASK;
 342        if (mode & SPI_CPOL)
 343                confr |= ZYNQ_SPI_CR_CPOL_MASK;
 344
 345        writel(confr, &regs->cr);
 346        priv->mode = mode;
 347
 348        debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
 349
 350        return 0;
 351}
 352
 353static const struct dm_spi_ops zynq_spi_ops = {
 354        .claim_bus      = zynq_spi_claim_bus,
 355        .release_bus    = zynq_spi_release_bus,
 356        .xfer           = zynq_spi_xfer,
 357        .set_speed      = zynq_spi_set_speed,
 358        .set_mode       = zynq_spi_set_mode,
 359};
 360
 361static const struct udevice_id zynq_spi_ids[] = {
 362        { .compatible = "xlnx,zynq-spi-r1p6" },
 363        { .compatible = "cdns,spi-r1p6" },
 364        { }
 365};
 366
 367U_BOOT_DRIVER(zynq_spi) = {
 368        .name   = "zynq_spi",
 369        .id     = UCLASS_SPI,
 370        .of_match = zynq_spi_ids,
 371        .ops    = &zynq_spi_ops,
 372        .ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
 373        .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
 374        .priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
 375        .probe  = zynq_spi_probe,
 376};
 377