LXR uboot/drivers/usb/host/ehci-fsl.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
   4 *
   5 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
   6 *
   7 * Author: Tor Krill tor@excito.com
   8 */
   9
  10#include <common.h>
  11#include <env.h>
  12#include <pci.h>
  13#include <usb.h>
  14#include <asm/io.h>
  15#include <usb/ehci-ci.h>
  16#include <hwconfig.h>
  17#include <fsl_usb.h>
  18#include <fdt_support.h>
  19#include <dm.h>
  20
  21#include "ehci.h"
  22
  23DECLARE_GLOBAL_DATA_PTR;
  24
  25#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  26#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  27#endif
  28
  29#if CONFIG_IS_ENABLED(DM_USB)
  30struct ehci_fsl_priv {
  31        struct ehci_ctrl ehci;
  32        fdt_addr_t hcd_base;
  33        char *phy_type;
  34};
  35#endif
  36
  37static void set_txfifothresh(struct usb_ehci *, u32);
  38#if CONFIG_IS_ENABLED(DM_USB)
  39static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
  40                  struct ehci_hccr *hccr, struct ehci_hcor *hcor);
  41#else
  42static int ehci_fsl_init(int index, struct usb_ehci *ehci,
  43                         struct ehci_hccr *hccr, struct ehci_hcor *hcor);
  44#endif
  45
  46/* Check USB PHY clock valid */
  47static int usb_phy_clk_valid(struct usb_ehci *ehci)
  48{
  49        if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
  50                        in_be32(&ehci->prictrl))) {
  51                printf("USB PHY clock invalid!\n");
  52                return 0;
  53        } else {
  54                return 1;
  55        }
  56}
  57
  58#if CONFIG_IS_ENABLED(DM_USB)
  59static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
  60{
  61        struct ehci_fsl_priv *priv = dev_get_priv(dev);
  62        const void *prop;
  63
  64        prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
  65                           NULL);
  66        if (prop) {
  67                priv->phy_type = (char *)prop;
  68                debug("phy_type %s\n", priv->phy_type);
  69        }
  70
  71        return 0;
  72}
  73
  74static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
  75{
  76        struct usb_ehci *ehci = NULL;
  77        struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
  78                                                   ehci);
  79#ifdef CONFIG_PPC
  80        ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
  81#else
  82        ehci = (struct usb_ehci *)priv->hcd_base;
  83#endif
  84
  85        if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
  86                return -ENXIO;
  87
  88        return 0;
  89}
  90
  91static const struct ehci_ops fsl_ehci_ops = {
  92        .init_after_reset = ehci_fsl_init_after_reset,
  93};
  94
  95static int ehci_fsl_probe(struct udevice *dev)
  96{
  97        struct ehci_fsl_priv *priv = dev_get_priv(dev);
  98        struct usb_ehci *ehci = NULL;
  99        struct ehci_hccr *hccr;
 100        struct ehci_hcor *hcor;
 101        struct ehci_ctrl *ehci_ctrl = &priv->ehci;
 102
 103        /*
 104         * Get the base address for EHCI controller from the device node
 105         */
 106        priv->hcd_base = devfdt_get_addr(dev);
 107        if (priv->hcd_base == FDT_ADDR_T_NONE) {
 108                debug("Can't get the EHCI register base address\n");
 109                return -ENXIO;
 110        }
 111#ifdef CONFIG_PPC
 112        ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
 113#else
 114        ehci = (struct usb_ehci *)priv->hcd_base;
 115#endif
 116        hccr = (struct ehci_hccr *)(&ehci->caplength);
 117        hcor = (struct ehci_hcor *)
 118                ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 119
 120        ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
 121
 122        if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
 123                return -ENXIO;
 124
 125        debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
 126              (void *)hccr, (void *)hcor,
 127              HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 128
 129        return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
 130}
 131
 132static const struct udevice_id ehci_usb_ids[] = {
 133        { .compatible = "fsl-usb2-mph", },
 134        { .compatible = "fsl-usb2-dr", },
 135        { }
 136};
 137
 138U_BOOT_DRIVER(ehci_fsl) = {
 139        .name   = "ehci_fsl",
 140        .id     = UCLASS_USB,
 141        .of_match = ehci_usb_ids,
 142        .ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
 143        .probe = ehci_fsl_probe,
 144        .remove = ehci_deregister,
 145        .ops    = &ehci_usb_ops,
 146        .platdata_auto_alloc_size = sizeof(struct usb_platdata),
 147        .priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
 148        .flags  = DM_FLAG_ALLOC_PRIV_DMA,
 149};
 150#else
 151/*
 152 * Create the appropriate control structures to manage
 153 * a new EHCI host controller.
 154 *
 155 * Excerpts from linux ehci fsl driver.
 156 */
 157int ehci_hcd_init(int index, enum usb_init_type init,
 158                struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 159{
 160        struct ehci_ctrl *ehci_ctrl = container_of(hccr,
 161                                        struct ehci_ctrl, hccr);
 162        struct usb_ehci *ehci = NULL;
 163
 164        switch (index) {
 165        case 0:
 166                ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 167                break;
 168        case 1:
 169                ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
 170                break;
 171        default:
 172                printf("ERROR: wrong controller index!!\n");
 173                return -EINVAL;
 174        };
 175
 176        *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 177        *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
 178                        HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 179
 180        ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
 181
 182        return ehci_fsl_init(index, ehci, *hccr, *hcor);
 183}
 184
 185/*
 186 * Destroy the appropriate control structures corresponding
 187 * the the EHCI host controller.
 188 */
 189int ehci_hcd_stop(int index)
 190{
 191        return 0;
 192}
 193#endif
 194
 195#if CONFIG_IS_ENABLED(DM_USB)
 196static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
 197                  struct ehci_hccr *hccr, struct ehci_hcor *hcor)
 198#else
 199static int ehci_fsl_init(int index, struct usb_ehci *ehci,
 200                         struct ehci_hccr *hccr, struct ehci_hcor *hcor)
 201#endif
 202{
 203        const char *phy_type = NULL;
 204#if !CONFIG_IS_ENABLED(DM_USB)
 205        size_t len;
 206        char current_usb_controller[5];
 207#endif
 208#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 209        char usb_phy[5];
 210
 211        usb_phy[0] = '\0';
 212#endif
 213        if (has_erratum_a007075()) {
 214                /*
 215                 * A 5ms delay is needed after applying soft-reset to the
 216                 * controller to let external ULPI phy come out of reset.
 217                 * This delay needs to be added before re-initializing
 218                 * the controller after soft-resetting completes
 219                 */
 220                mdelay(5);
 221        }
 222
 223        /* Set to Host mode */
 224        setbits_le32(&ehci->usbmode, CM_HOST);
 225
 226        out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
 227        out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
 228
 229        /* Init phy */
 230#if CONFIG_IS_ENABLED(DM_USB)
 231        if (priv->phy_type)
 232                phy_type = priv->phy_type;
 233#else
 234        memset(current_usb_controller, '\0', 5);
 235        snprintf(current_usb_controller, sizeof(current_usb_controller),
 236                 "usb%d", index+1);
 237
 238        if (hwconfig_sub(current_usb_controller, "phy_type"))
 239                phy_type = hwconfig_subarg(current_usb_controller,
 240                                "phy_type", &len);
 241#endif
 242        else
 243                phy_type = env_get("usb_phy_type");
 244
 245        if (!phy_type) {
 246#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 247                /* if none specified assume internal UTMI */
 248                strcpy(usb_phy, "utmi");
 249                phy_type = usb_phy;
 250#else
 251                printf("WARNING: USB phy type not defined !!\n");
 252                return -1;
 253#endif
 254        }
 255
 256        if (!strncmp(phy_type, "utmi", 4)) {
 257#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
 258                clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
 259                                PHY_CLK_SEL_UTMI);
 260                clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
 261                                UTMI_PHY_EN);
 262                udelay(1000); /* delay required for PHY Clk to appear */
 263#endif
 264                out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
 265                clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
 266                                USB_EN);
 267        } else {
 268                clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
 269                                PHY_CLK_SEL_ULPI);
 270                clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
 271                                CONTROL_REGISTER_W1C_MASK, USB_EN);
 272                udelay(1000); /* delay required for PHY Clk to appear */
 273                if (!usb_phy_clk_valid(ehci))
 274                        return -EINVAL;
 275                out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
 276        }
 277
 278        out_be32(&ehci->prictrl, 0x0000000c);
 279        out_be32(&ehci->age_cnt_limit, 0x00000040);
 280        out_be32(&ehci->sictrl, 0x00000001);
 281
 282        in_le32(&ehci->usbmode);
 283
 284        if (has_erratum_a007798())
 285                set_txfifothresh(ehci, TXFIFOTHRESH);
 286
 287        if (has_erratum_a004477()) {
 288                /*
 289                 * When reset is issued while any ULPI transaction is ongoing
 290                 * then it may result to corruption of ULPI Function Control
 291                 * Register which eventually causes phy clock to enter low
 292                 * power mode which stops the clock. Thus delay is required
 293                 * before reset to let ongoing ULPI transaction complete.
 294                 */
 295                udelay(1);
 296        }
 297        return 0;
 298}
 299
 300/*
 301 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
 302 * to counter DDR latencies in writing data into Tx buffer.
 303 * This prevents Tx buffer from getting underrun
 304 */
 305static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
 306{
 307        u32 cmd;
 308        cmd = ehci_readl(&ehci->txfilltuning);
 309        cmd &= ~TXFIFO_THRESH_MASK;
 310        cmd |= TXFIFO_THRESH(txfifo_thresh);
 311        ehci_writel(&ehci->txfilltuning, cmd);
 312}
 313