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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
12#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
13#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
14#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
15#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
16
17#ifndef CONFIG_SYS_MONITOR_BASE
18#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
19#endif
20
21
22
23
24#define CONFIG_E300 1
25
26
27
28
29#define CONFIG_SYS_SICRH 0x00000000
30#define CONFIG_SYS_SICRL 0x00000000
31
32#define CONFIG_HWCONFIG
33
34
35
36
37#define CONFIG_SYS_SDRAM_BASE 0x00000000
38#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
39#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
40 | DDRCDR_PZ_LOZ \
41 | DDRCDR_NZ_LOZ \
42 | DDRCDR_ODT \
43 | DDRCDR_Q_DRN)
44
45
46
47
48
49#define CONFIG_SYS_DDR_SIZE 128
50#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
51#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
52 | CSCONFIG_ODT_RD_NEVER \
53 | CSCONFIG_ODT_WR_ONLY_CURRENT \
54 | CSCONFIG_ROW_BIT_13 \
55 | CSCONFIG_COL_BIT_10)
56
57#define CONFIG_SYS_DDR_TIMING_3 0x00000000
58#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
59 | (0 << TIMING_CFG0_WRT_SHIFT) \
60 | (0 << TIMING_CFG0_RRT_SHIFT) \
61 | (0 << TIMING_CFG0_WWT_SHIFT) \
62 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
63 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
64 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
65 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
66
67#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
68 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
69 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
70 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
71 | (6 << TIMING_CFG1_REFREC_SHIFT) \
72 | (2 << TIMING_CFG1_WRREC_SHIFT) \
73 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
74 | (2 << TIMING_CFG1_WRTORD_SHIFT))
75
76#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
77 | (4 << TIMING_CFG2_CPO_SHIFT) \
78 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
79 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
80 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
81 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
82 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
83
84#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
85 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
86
87#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
88 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
89 | SDRAM_CFG_DBW_32)
90
91#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
92#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
93 | (0x0232 << SDRAM_MODE_SD_SHIFT))
94
95#define CONFIG_SYS_DDR_MODE2 0x00000000
96
97
98
99
100#undef CONFIG_SYS_DRAM_TEST
101#define CONFIG_SYS_MEMTEST_START 0x00040000
102#define CONFIG_SYS_MEMTEST_END 0x00140000
103
104
105
106
107#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
108#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
109
110
111
112
113#define CONFIG_SYS_INIT_RAM_LOCK 1
114#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
115#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
116#define CONFIG_SYS_GBL_DATA_OFFSET \
117 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
118
119#define CONFIG_FSL_ELBC
120
121
122
123
124#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
125
126#define CONFIG_SYS_FLASH_BASE 0xFE000000
127#define CONFIG_SYS_FLASH_SIZE 8
128
129#define CONFIG_SYS_MAX_FLASH_BANKS 1
130
131#define CONFIG_SYS_MAX_FLASH_SECT 135
132
133#undef CONFIG_SYS_FLASH_CHECKSUM
134#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
135#define CONFIG_SYS_FLASH_WRITE_TOUT 500
136
137
138
139
140
141#ifdef CONFIG_NAND_SPL
142#define CONFIG_SYS_NAND_BASE 0xFFF00000
143#else
144#define CONFIG_SYS_NAND_BASE 0xE0600000
145#endif
146
147#define CONFIG_MTD_PARTITION
148
149#define CONFIG_SYS_MAX_NAND_DEVICE 1
150#define CONFIG_NAND_FSL_ELBC 1
151#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
152#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
153
154#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
155#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
156#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
157#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
158#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
159
160
161
162
163#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
164#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
165
166#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
167 !defined(CONFIG_NAND_SPL)
168#define CONFIG_SYS_RAMBOOT
169#else
170#undef CONFIG_SYS_RAMBOOT
171#endif
172
173
174
175
176#define CONFIG_SYS_NS16550_SERIAL
177#define CONFIG_SYS_NS16550_REG_SIZE 1
178#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
179
180#define CONFIG_SYS_BAUDRATE_TABLE \
181 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
182
183#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
184#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
185
186
187#define CONFIG_SYS_I2C
188#define CONFIG_SYS_I2C_FSL
189#define CONFIG_SYS_FSL_I2C_SPEED 400000
190#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
191#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
192#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
193
194
195
196
197#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
198
199
200
201
202#define CONFIG_RTC_DS1337
203#define CONFIG_SYS_I2C_RTC_ADDR 0x68
204
205
206
207
208
209#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
210#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
211#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
212#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
213#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
214#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000
215#define CONFIG_SYS_PCI_IO_BASE 0x00000000
216#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
217#define CONFIG_SYS_PCI_IO_SIZE 0x100000
218
219#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
220#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
221#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
222
223#define CONFIG_SYS_PCIE1_BASE 0xA0000000
224#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
225#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
226#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
227#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
228#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
229#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
230#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
231#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
232
233#define CONFIG_SYS_PCIE2_BASE 0xC0000000
234#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
235#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
236#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
237#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
238#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
239#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
240#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
241#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
242
243#define CONFIG_PCI_INDIRECT_BRIDGE
244#define CONFIG_PCIE
245
246#define CONFIG_EEPRO100
247#undef CONFIG_PCI_SCAN_SHOW
248#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
249
250#define CONFIG_HAS_FSL_DR_USB
251#define CONFIG_SYS_SCCR_USBDRCM 3
252
253#define CONFIG_USB_EHCI_FSL
254#define CONFIG_USB_PHY_TYPE "utmi"
255#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
256
257
258
259
260#define CONFIG_SYS_TSEC1_OFFSET 0x24000
261#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
262#define CONFIG_SYS_TSEC2_OFFSET 0x25000
263#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
264
265
266
267
268#define CONFIG_TSEC1 1
269#define CONFIG_TSEC1_NAME "eTSEC0"
270#define CONFIG_TSEC2 1
271#define CONFIG_TSEC2_NAME "eTSEC1"
272#define TSEC1_PHY_ADDR 0
273#define TSEC2_PHY_ADDR 1
274#define TSEC1_PHYIDX 0
275#define TSEC2_PHYIDX 0
276#define TSEC1_FLAGS TSEC_GIGABIT
277#define TSEC2_FLAGS TSEC_GIGABIT
278
279
280#define CONFIG_ETHPRIME "eTSEC1"
281
282
283
284
285#define CONFIG_SYS_SATA_MAX_DEVICE 2
286#define CONFIG_SATA1
287#define CONFIG_SYS_SATA1_OFFSET 0x18000
288#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
289#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
290#define CONFIG_SATA2
291#define CONFIG_SYS_SATA2_OFFSET 0x19000
292#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
293#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
294
295#ifdef CONFIG_FSL_SATA
296#define CONFIG_LBA48
297#endif
298
299
300
301
302
303#define CONFIG_LOADS_ECHO 1
304#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
305
306
307
308
309#define CONFIG_BOOTP_BOOTFILESIZE
310
311
312
313
314
315#undef CONFIG_WATCHDOG
316
317
318
319
320#define CONFIG_SYS_LOAD_ADDR 0x2000000
321
322
323
324
325
326
327#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
328#define CONFIG_SYS_BOOTM_LEN (64 << 20)
329
330
331
332
333
334#if defined(CONFIG_CMD_KGDB)
335#define CONFIG_KGDB_BAUDRATE 230400
336#endif
337
338
339
340
341
342#define CONFIG_ENV_OVERWRITE
343
344#if defined(CONFIG_TSEC_ENET)
345#define CONFIG_HAS_ETH0
346#define CONFIG_HAS_ETH1
347#endif
348
349#define CONFIG_LOADADDR 800000
350
351#define CONFIG_EXTRA_ENV_SETTINGS \
352 "netdev=eth0\0" \
353 "consoledev=ttyS0\0" \
354 "ramdiskaddr=1000000\0" \
355 "ramdiskfile=ramfs.83xx\0" \
356 "fdtaddr=780000\0" \
357 "fdtfile=mpc8315erdb.dtb\0" \
358 "usb_phy_type=utmi\0" \
359 ""
360
361#define CONFIG_NFSBOOTCOMMAND \
362 "setenv bootargs root=/dev/nfs rw " \
363 "nfsroot=$serverip:$rootpath " \
364 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
365 "$netdev:off " \
366 "console=$consoledev,$baudrate $othbootargs;" \
367 "tftp $loadaddr $bootfile;" \
368 "tftp $fdtaddr $fdtfile;" \
369 "bootm $loadaddr - $fdtaddr"
370
371#define CONFIG_RAMBOOTCOMMAND \
372 "setenv bootargs root=/dev/ram rw " \
373 "console=$consoledev,$baudrate $othbootargs;" \
374 "tftp $ramdiskaddr $ramdiskfile;" \
375 "tftp $loadaddr $bootfile;" \
376 "tftp $fdtaddr $fdtfile;" \
377 "bootm $loadaddr $ramdiskaddr $fdtaddr"
378
379#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
380
381#endif
382