1
2
3
4
5
6
7
8
9
10
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_SYS_SRIO
16#define CONFIG_SRIO1
17
18#define CONFIG_PCI1
19#define CONFIG_PCIE1
20#undef CONFIG_PCI2
21#define CONFIG_SYS_PCI_64BIT 1
22
23#define CONFIG_ENV_OVERWRITE
24#define CONFIG_INTERRUPTS
25
26#define CONFIG_FSL_VIA
27
28#ifndef __ASSEMBLY__
29extern unsigned long get_clock_freq(void);
30#endif
31#define CONFIG_SYS_CLK_FREQ get_clock_freq()
32
33
34
35
36#define CONFIG_L2_CACHE
37#define CONFIG_BTB
38
39
40
41
42#define CONFIG_ENABLE_36BIT_PHYS 1
43
44#ifdef CONFIG_PHYS_64BIT
45#define CONFIG_ADDR_MAP
46#define CONFIG_SYS_NUM_ADDR_MAP 16
47#endif
48
49#define CONFIG_SYS_MEMTEST_START 0x00200000
50#define CONFIG_SYS_MEMTEST_END 0x00400000
51
52#define CONFIG_SYS_CCSRBAR 0xe0000000
53#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
54
55
56#define CONFIG_SPD_EEPROM
57#define CONFIG_DDR_SPD
58
59#define CONFIG_DDR_ECC
60#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
61#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
62
63#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
64#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
65
66#define CONFIG_DIMM_SLOTS_PER_CTLR 1
67#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
68
69
70#define SPD_EEPROM_ADDRESS 0x51
71
72
73#ifndef CONFIG_SPD_EEPROM
74#error ("CONFIG_SPD_EEPROM is required")
75#endif
76
77#undef CONFIG_CLOCKS_IN_MHZ
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143#define CONFIG_SYS_FLASH_BASE 0xff000000
144#ifdef CONFIG_PHYS_64BIT
145#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
146#else
147#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
148#endif
149
150#define CONFIG_SYS_BR0_PRELIM \
151 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
152#define CONFIG_SYS_BR1_PRELIM \
153 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
154
155#define CONFIG_SYS_OR0_PRELIM 0xff806e65
156#define CONFIG_SYS_OR1_PRELIM 0xff806e65
157
158#define CONFIG_SYS_FLASH_BANKS_LIST \
159 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
160#define CONFIG_SYS_MAX_FLASH_BANKS 2
161#define CONFIG_SYS_MAX_FLASH_SECT 128
162#undef CONFIG_SYS_FLASH_CHECKSUM
163#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
164#define CONFIG_SYS_FLASH_WRITE_TOUT 500
165
166#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
167
168#define CONFIG_SYS_FLASH_EMPTY_INFO
169
170#define CONFIG_HWCONFIG
171
172
173
174
175#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
176#ifdef CONFIG_PHYS_64BIT
177#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
178#else
179#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
180#endif
181#define CONFIG_SYS_LBC_SDRAM_SIZE 64
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201#define CONFIG_SYS_BR2_PRELIM \
202 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
203 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219#define CONFIG_SYS_OR2_PRELIM 0xfc006901
220
221#define CONFIG_SYS_LBC_LCRR 0x00030004
222#define CONFIG_SYS_LBC_LBCR 0x00000000
223#define CONFIG_SYS_LBC_LSRT 0x20000000
224#define CONFIG_SYS_LBC_MRTPR 0x00000000
225
226
227
228
229
230
231
232#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
233 | LSDMR_PRETOACT7 \
234 | LSDMR_ACTTORW7 \
235 | LSDMR_BL8 \
236 | LSDMR_WRC4 \
237 | LSDMR_CL3 \
238 | LSDMR_RFEN \
239 )
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271#define CONFIG_FSL_CADMUS
272
273#define CADMUS_BASE_ADDR 0xf8000000
274#ifdef CONFIG_PHYS_64BIT
275#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
276#else
277#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
278#endif
279#define CONFIG_SYS_BR3_PRELIM \
280 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
281#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
282
283#define CONFIG_SYS_INIT_RAM_LOCK 1
284#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
285#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
286
287#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
288#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
289
290#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
291#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
292
293
294#define CONFIG_SYS_NS16550_SERIAL
295#define CONFIG_SYS_NS16550_REG_SIZE 1
296#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
297
298#define CONFIG_SYS_BAUDRATE_TABLE \
299 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
300
301#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
302#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
303
304
305
306
307#define CONFIG_SYS_I2C
308#define CONFIG_SYS_I2C_FSL
309#define CONFIG_SYS_FSL_I2C_SPEED 400000
310#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
311#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
312#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
313
314
315#define CONFIG_ID_EEPROM
316#define CONFIG_SYS_I2C_EEPROM_CCID
317#define CONFIG_SYS_ID_EEPROM
318#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
319#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
320
321
322
323
324
325#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
326#ifdef CONFIG_PHYS_64BIT
327#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
328#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
329#else
330#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
331#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
332#endif
333#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
334#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
335#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
336#ifdef CONFIG_PHYS_64BIT
337#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
338#else
339#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
340#endif
341#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
342
343#ifdef CONFIG_PCIE1
344#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
345#ifdef CONFIG_PHYS_64BIT
346#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
347#else
348#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
349#endif
350#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
351#ifdef CONFIG_PHYS_64BIT
352#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
353#else
354#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
355#endif
356#endif
357
358
359
360
361#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
362#ifdef CONFIG_PHYS_64BIT
363#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
364#else
365#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
366#endif
367#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
368
369#ifdef CONFIG_LEGACY
370#define BRIDGE_ID 17
371#define VIA_ID 2
372#else
373#define BRIDGE_ID 28
374#define VIA_ID 4
375#endif
376
377#if defined(CONFIG_PCI)
378#undef CONFIG_EEPRO100
379#undef CONFIG_TULIP
380
381#if !defined(CONFIG_DM_PCI)
382#define CONFIG_FSL_PCI_INIT 1
383#define CONFIG_PCI_INDIRECT_BRIDGE 1
384#define CONFIG_SYS_PCIE1_NAME "Slot"
385#ifdef CONFIG_PHYS_64BIT
386#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
387#else
388#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
389#endif
390#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
391#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
392#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000
393#endif
394
395#define CONFIG_PCI_SCAN_SHOW
396
397#endif
398
399#if defined(CONFIG_TSEC_ENET)
400
401#define CONFIG_TSEC1 1
402#define CONFIG_TSEC1_NAME "eTSEC0"
403#define CONFIG_TSEC2 1
404#define CONFIG_TSEC2_NAME "eTSEC1"
405#define CONFIG_TSEC3 1
406#define CONFIG_TSEC3_NAME "eTSEC2"
407#define CONFIG_TSEC4
408#define CONFIG_TSEC4_NAME "eTSEC3"
409#undef CONFIG_MPC85XX_FEC
410
411#define TSEC1_PHY_ADDR 0
412#define TSEC2_PHY_ADDR 1
413#define TSEC3_PHY_ADDR 2
414#define TSEC4_PHY_ADDR 3
415
416#define TSEC1_PHYIDX 0
417#define TSEC2_PHYIDX 0
418#define TSEC3_PHYIDX 0
419#define TSEC4_PHYIDX 0
420#define TSEC1_FLAGS TSEC_GIGABIT
421#define TSEC2_FLAGS TSEC_GIGABIT
422#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
423#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
424
425
426#define CONFIG_ETHPRIME "eTSEC0"
427#endif
428
429
430
431
432
433#define CONFIG_LOADS_ECHO 1
434#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
435
436
437
438
439#define CONFIG_BOOTP_BOOTFILESIZE
440
441#undef CONFIG_WATCHDOG
442
443
444
445
446#define CONFIG_SYS_LOAD_ADDR 0x2000000
447
448
449
450
451
452
453#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
454#define CONFIG_SYS_BOOTM_LEN (64 << 20)
455
456#if defined(CONFIG_CMD_KGDB)
457#define CONFIG_KGDB_BAUDRATE 230400
458#endif
459
460
461
462
463#if defined(CONFIG_TSEC_ENET)
464#define CONFIG_HAS_ETH0
465#define CONFIG_HAS_ETH1
466#define CONFIG_HAS_ETH2
467#define CONFIG_HAS_ETH3
468#endif
469
470#define CONFIG_IPADDR 192.168.1.253
471
472#define CONFIG_HOSTNAME "unknown"
473#define CONFIG_ROOTPATH "/nfsroot"
474#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
475#define CONFIG_UBOOTPATH 8548cds/u-boot.bin
476
477#define CONFIG_SERVERIP 192.168.1.1
478#define CONFIG_GATEWAYIP 192.168.1.1
479#define CONFIG_NETMASK 255.255.255.0
480
481#define CONFIG_LOADADDR 1000000
482
483#define CONFIG_EXTRA_ENV_SETTINGS \
484 "hwconfig=fsl_ddr:ecc=off\0" \
485 "netdev=eth0\0" \
486 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
487 "tftpflash=tftpboot $loadaddr $uboot; " \
488 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
489 " +$filesize; " \
490 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
491 " +$filesize; " \
492 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
493 " $filesize; " \
494 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
495 " +$filesize; " \
496 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
497 " $filesize\0" \
498 "consoledev=ttyS1\0" \
499 "ramdiskaddr=2000000\0" \
500 "ramdiskfile=ramdisk.uboot\0" \
501 "fdtaddr=1e00000\0" \
502 "fdtfile=mpc8548cds.dtb\0"
503
504#define CONFIG_NFSBOOTCOMMAND \
505 "setenv bootargs root=/dev/nfs rw " \
506 "nfsroot=$serverip:$rootpath " \
507 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
508 "console=$consoledev,$baudrate $othbootargs;" \
509 "tftp $loadaddr $bootfile;" \
510 "tftp $fdtaddr $fdtfile;" \
511 "bootm $loadaddr - $fdtaddr"
512
513#define CONFIG_RAMBOOTCOMMAND \
514 "setenv bootargs root=/dev/ram rw " \
515 "console=$consoledev,$baudrate $othbootargs;" \
516 "tftp $ramdiskaddr $ramdiskfile;" \
517 "tftp $loadaddr $bootfile;" \
518 "tftp $fdtaddr $fdtfile;" \
519 "bootm $loadaddr $ramdiskaddr $fdtaddr"
520
521#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
522
523#endif
524