LXR uboot/include/configs/db-mv784mp-gp.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
   4 */
   5
   6#ifndef _CONFIG_DB_MV7846MP_GP_H
   7#define _CONFIG_DB_MV7846MP_GP_H
   8
   9/*
  10 * High Level Configuration Options (easy to change)
  11 */
  12#define CONFIG_DB_784MP_GP              /* Board target name for DDR training */
  13
  14/*
  15 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  16 * for DDR ECC byte filling in the SPL before loading the main
  17 * U-Boot into it.
  18 */
  19#define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  20
  21/* I2C */
  22#define CONFIG_SYS_I2C
  23#define CONFIG_SYS_I2C_MVTWSI
  24#define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  25#define CONFIG_SYS_I2C_SLAVE            0x0
  26#define CONFIG_SYS_I2C_SPEED            100000
  27
  28/* USB/EHCI configuration */
  29#define CONFIG_EHCI_IS_TDI
  30#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  31
  32/* Environment in SPI NOR flash */
  33
  34#define PHY_ANEG_TIMEOUT        8000    /* PHY needs a longer aneg time */
  35
  36/* SATA support */
  37#define CONFIG_SYS_SATA_MAX_DEVICE      2
  38#define CONFIG_LBA48
  39
  40/* PCIe support */
  41#ifndef CONFIG_SPL_BUILD
  42#define CONFIG_PCI_SCAN_SHOW
  43#endif
  44
  45/* NAND */
  46#define CONFIG_SYS_NAND_ONFI_DETECTION
  47
  48/*
  49 * mv-common.h should be defined after CMD configs since it used them
  50 * to enable certain macros
  51 */
  52#include "mv-common.h"
  53
  54/*
  55 * Memory layout while starting into the bin_hdr via the
  56 * BootROM:
  57 *
  58 * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
  59 * 0x4000.4030                  bin_hdr start address
  60 * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
  61 * 0x4007.fffc                  BootROM stack top
  62 *
  63 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  64 * L2 cache thus cannot be used.
  65 */
  66
  67/* SPL */
  68/* Defines for SPL */
  69#define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
  70
  71#define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
  72#define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
  73
  74#ifdef CONFIG_SPL_BUILD
  75#define CONFIG_SYS_MALLOC_SIMPLE
  76#endif
  77
  78#define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
  79#define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
  80
  81/* SPL related SPI defines */
  82#define CONFIG_SYS_U_BOOT_OFFS          CONFIG_SYS_SPI_U_BOOT_OFFS
  83
  84/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
  85#define CONFIG_SPD_EEPROM               0x4e
  86#define CONFIG_BOARD_ECC_SUPPORT        /* this board supports ECC */
  87
  88#endif /* _CONFIG_DB_MV7846MP_GP_H */
  89