LXR uboot/include/configs/p1

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2013 Freescale Semiconductor, Inc.
   4 */
   5
   6/*
   7 * QorIQ P1 Tower boards configuration file
   8 */
   9#ifndef __CONFIG_H
  10#define __CONFIG_H
  11
  12#if defined(CONFIG_TWR_P1025)
  13#define CONFIG_BOARDNAME "TWR-P1025"
  14#define CONFIG_PHY_ATHEROS
  15#define CONFIG_SYS_LBC_LBCR     0x00080000      /* Conversion of LBC addr */
  16#define CONFIG_SYS_LBC_LCRR     0x80000002      /* LB clock ratio reg */
  17#endif
  18
  19#ifdef CONFIG_SDCARD
  20#define CONFIG_RAMBOOT_SDCARD
  21#define CONFIG_SYS_RAMBOOT
  22#define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  23#endif
  24
  25#ifndef CONFIG_RESET_VECTOR_ADDRESS
  26#define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  27#endif
  28
  29#ifndef CONFIG_SYS_MONITOR_BASE
  30#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  31#endif
  32
  33#define CONFIG_PCIE1    /* PCIE controller 1 (slot 1) */
  34#define CONFIG_PCIE2    /* PCIE controller 2 (slot 2) */
  35#define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  36#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  37#define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  38
  39#define CONFIG_ENV_OVERWRITE
  40
  41#define CONFIG_SYS_SATA_MAX_DEVICE      2
  42#define CONFIG_LBA48
  43
  44#ifndef __ASSEMBLY__
  45extern unsigned long get_board_sys_clk(unsigned long dummy);
  46#endif
  47#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /*sysclk for TWR-P1025 */
  48
  49#define CONFIG_DDR_CLK_FREQ     66666666
  50
  51#define CONFIG_HWCONFIG
  52/*
  53 * These can be toggled for performance analysis, otherwise use default.
  54 */
  55#define CONFIG_L2_CACHE
  56#define CONFIG_BTB
  57
  58#define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  59#define CONFIG_SYS_MEMTEST_END          0x1fffffff
  60
  61#define CONFIG_SYS_CCSRBAR              0xffe00000
  62#define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  63
  64/* DDR Setup */
  65
  66#define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_512M
  67#define CONFIG_CHIP_SELECTS_PER_CTRL    1
  68
  69#define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  70#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  71#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  72
  73#define CONFIG_DIMM_SLOTS_PER_CTLR      1
  74
  75/* Default settings for DDR3 */
  76#define CONFIG_SYS_DDR_CS0_BNDS         0x0000001f
  77#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
  78#define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
  79#define CONFIG_SYS_DDR_CS1_BNDS         0x00000000
  80#define CONFIG_SYS_DDR_CS1_CONFIG       0x00000000
  81#define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
  82
  83#define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
  84#define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
  85#define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
  86#define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
  87
  88#define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
  89#define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655a608
  90#define CONFIG_SYS_DDR_SR_CNTR          0x00000000
  91#define CONFIG_SYS_DDR_RCW_1            0x00000000
  92#define CONFIG_SYS_DDR_RCW_2            0x00000000
  93#define CONFIG_SYS_DDR_CONTROL          0xc70c0000      /* Type = DDR3  */
  94#define CONFIG_SYS_DDR_CONTROL_2        0x04401050
  95#define CONFIG_SYS_DDR_TIMING_4         0x00220001
  96#define CONFIG_SYS_DDR_TIMING_5         0x03402400
  97
  98#define CONFIG_SYS_DDR_TIMING_3         0x00020000
  99#define CONFIG_SYS_DDR_TIMING_0         0x00220004
 100#define CONFIG_SYS_DDR_TIMING_1         0x5c5b6544
 101#define CONFIG_SYS_DDR_TIMING_2         0x0fa880de
 102#define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
 103#define CONFIG_SYS_DDR_MODE_1           0x80461320
 104#define CONFIG_SYS_DDR_MODE_2           0x00008000
 105#define CONFIG_SYS_DDR_INTERVAL         0x09480000
 106
 107/*
 108 * Memory map
 109 *
 110 * 0x0000_0000 0x1fff_ffff      DDR             Up to 512MB cacheable
 111 * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1.5G non-cacheable(PCIe * 3)
 112 * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
 113 *
 114 * Localbus
 115 * 0xe000_0000 0xe002_0000      SSD1289         128K non-cacheable
 116 * 0xec00_0000 0xefff_ffff      FLASH           Up to 64M non-cacheable
 117 *
 118 * 0xff90_0000 0xff97_ffff      L2 SRAM         Up to 512K cacheable
 119 * 0xffd0_0000 0xffd0_3fff      init ram        16K Cacheable
 120 * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
 121 */
 122
 123/*
 124 * Local Bus Definitions
 125 */
 126#define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 127#define CONFIG_SYS_FLASH_BASE           0xec000000
 128
 129#define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 130
 131#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
 132        | BR_PS_16 | BR_V)
 133
 134#define CONFIG_FLASH_OR_PRELIM  0xfc0000b1
 135
 136#define CONFIG_SYS_SSD_BASE     0xe0000000
 137#define CONFIG_SYS_SSD_BASE_PHYS        CONFIG_SYS_SSD_BASE
 138#define CONFIG_SSD_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
 139                                        BR_PS_16 | BR_V)
 140#define CONFIG_SSD_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 141                                 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
 142                                 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 143
 144#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
 145#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
 146
 147#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 148#define CONFIG_SYS_FLASH_QUIET_TEST
 149#define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 150
 151#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 152
 153#undef CONFIG_SYS_FLASH_CHECKSUM
 154#define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 155#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 156
 157#define CONFIG_SYS_FLASH_EMPTY_INFO
 158
 159#define CONFIG_SYS_INIT_RAM_LOCK
 160#define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000
 161/* Initial L1 address */
 162#define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 163#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 164#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 165/* Size of used area in RAM */
 166#define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 167
 168#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 169                                        GENERATED_GBL_DATA_SIZE)
 170#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 171
 172#define CONFIG_SYS_MONITOR_LEN  (768 * 1024)
 173#define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
 174
 175#define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 176#define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 177
 178/* Serial Port
 179 * open - index 2
 180 * shorted - index 1
 181 */
 182#undef CONFIG_SERIAL_SOFTWARE_FIFO
 183#define CONFIG_SYS_NS16550_SERIAL
 184#define CONFIG_SYS_NS16550_REG_SIZE     1
 185#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 186
 187#define CONFIG_SYS_BAUDRATE_TABLE       \
 188        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 189
 190#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 191#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 192
 193/* I2C */
 194#define CONFIG_SYS_I2C
 195#define CONFIG_SYS_I2C_FSL                      /* Use FSL common I2C driver */
 196#define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C spd and slave address */
 197#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 198#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 199#define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 200
 201/*
 202 * I2C2 EEPROM
 203 */
 204#define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C spd and slave address */
 205#define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 206#define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 207
 208#define CONFIG_SYS_I2C_PCA9555_ADDR     0x23
 209
 210/* enable read and write access to EEPROM */
 211#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 212#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 213#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 214
 215#if defined(CONFIG_PCI)
 216/*
 217 * General PCI
 218 * Memory space is mapped 1-1, but I/O space must start from 0.
 219 */
 220
 221/* controller 2, direct to uli, tgtid 2, Base address 9000 */
 222#define CONFIG_SYS_PCIE2_NAME           "TWR-ELEV PCIe SLOT"
 223#define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 224#define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 225#define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 226#define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 227#define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 228#define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 229#define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 230#define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 231
 232/* controller 1, tgtid 1, Base address a000 */
 233#define CONFIG_SYS_PCIE1_NAME           "mini PCIe SLOT"
 234#define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 235#define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 236#define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 237#define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 238#define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 239#define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 240#define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 241#define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 242
 243#define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 244#endif /* CONFIG_PCI */
 245
 246#if defined(CONFIG_TSEC_ENET)
 247
 248#define CONFIG_TSEC1
 249#define CONFIG_TSEC1_NAME       "eTSEC1"
 250#undef CONFIG_TSEC2
 251#undef CONFIG_TSEC2_NAME
 252#define CONFIG_TSEC3
 253#define CONFIG_TSEC3_NAME       "eTSEC3"
 254
 255#define TSEC1_PHY_ADDR  2
 256#define TSEC2_PHY_ADDR  0
 257#define TSEC3_PHY_ADDR  1
 258
 259#define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 260#define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 261#define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 262
 263#define TSEC1_PHYIDX    0
 264#define TSEC2_PHYIDX    0
 265#define TSEC3_PHYIDX    0
 266
 267#define CONFIG_ETHPRIME "eTSEC1"
 268
 269#define CONFIG_HAS_ETH0
 270#define CONFIG_HAS_ETH1
 271#undef CONFIG_HAS_ETH2
 272#endif /* CONFIG_TSEC_ENET */
 273
 274#ifdef CONFIG_QE
 275/* QE microcode/firmware address */
 276#define CONFIG_SYS_QE_FW_ADDR   0xefec0000
 277#define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 278#endif /* CONFIG_QE */
 279
 280#ifdef CONFIG_TWR_P1025
 281/*
 282 * QE UEC ethernet configuration
 283 */
 284#define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 285
 286#undef CONFIG_UEC_ETH
 287#define CONFIG_PHY_MODE_NEED_CHANGE
 288
 289#define CONFIG_UEC_ETH1 /* ETH1 */
 290#define CONFIG_HAS_ETH0
 291
 292#ifdef CONFIG_UEC_ETH1
 293#define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 294#define CONFIG_SYS_UEC1_RX_CLK  QE_CLK12 /* CLK12 for MII */
 295#define CONFIG_SYS_UEC1_TX_CLK  QE_CLK9 /* CLK9 for MII */
 296#define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 297#define CONFIG_SYS_UEC1_PHY_ADDR        0x18    /* 0x18 for MII */
 298#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
 299#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 300#endif /* CONFIG_UEC_ETH1 */
 301
 302#define CONFIG_UEC_ETH5 /* ETH5 */
 303#define CONFIG_HAS_ETH1
 304
 305#ifdef CONFIG_UEC_ETH5
 306#define CONFIG_SYS_UEC5_UCC_NUM 4       /* UCC5 */
 307#define CONFIG_SYS_UEC5_RX_CLK  QE_CLK_NONE
 308#define CONFIG_SYS_UEC5_TX_CLK  QE_CLK13 /* CLK 13 for RMII */
 309#define CONFIG_SYS_UEC5_ETH_TYPE        FAST_ETH
 310#define CONFIG_SYS_UEC5_PHY_ADDR        0x19    /* 0x19 for RMII */
 311#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 312#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
 313#endif /* CONFIG_UEC_ETH5 */
 314#endif /* CONFIG_TWR-P1025 */
 315
 316/*
 317 * Dynamic MTD Partition support with mtdparts
 318 */
 319
 320/*
 321 * Environment
 322 */
 323#ifdef CONFIG_SYS_RAMBOOT
 324#ifdef CONFIG_RAMBOOT_SDCARD
 325#define CONFIG_SYS_MMC_ENV_DEV  0
 326#endif
 327#endif
 328
 329#define CONFIG_LOADS_ECHO               /* echo on for serial download */
 330#define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 331
 332/*
 333 * USB
 334 */
 335#define CONFIG_HAS_FSL_DR_USB
 336
 337#if defined(CONFIG_HAS_FSL_DR_USB)
 338#ifdef CONFIG_USB_EHCI_HCD
 339#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 340#define CONFIG_USB_EHCI_FSL
 341#endif
 342#endif
 343
 344#ifdef CONFIG_MMC
 345#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 346#endif
 347
 348#undef CONFIG_WATCHDOG  /* watchdog disabled */
 349
 350/*
 351 * Miscellaneous configurable options
 352 */
 353#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 354
 355/*
 356 * For booting Linux, the board info and command line data
 357 * have to be in the first 64 MB of memory, since this is
 358 * the maximum mapped by the Linux kernel during initialization.
 359 */
 360#define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
 361#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 362
 363/*
 364 * Environment Configuration
 365 */
 366#define CONFIG_HOSTNAME         "unknown"
 367#define CONFIG_ROOTPATH         "/opt/nfsroot"
 368#define CONFIG_BOOTFILE         "uImage"
 369#define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 370
 371/* default location for tftp and bootm */
 372#define CONFIG_LOADADDR 1000000
 373
 374#define CONFIG_EXTRA_ENV_SETTINGS       \
 375"netdev=eth0\0" \
 376"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 377"loadaddr=1000000\0"    \
 378"bootfile=uImage\0"     \
 379"dtbfile=twr-p1025twr.dtb\0"    \
 380"ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 381"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0"   \
 382"tftpflash=tftpboot $loadaddr $uboot; " \
 383        "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 384        "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 385        "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 386        "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 387        "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 388"kernelflash=tftpboot $loadaddr $bootfile; "    \
 389        "protect off 0xefa80000 +$filesize; "   \
 390        "erase 0xefa80000 +$filesize; " \
 391        "cp.b $loadaddr 0xefa80000 $filesize; " \
 392        "protect on 0xefa80000 +$filesize; "    \
 393        "cmp.b $loadaddr 0xefa80000 $filesize\0"        \
 394"dtbflash=tftpboot $loadaddr $dtbfile; "        \
 395        "protect off 0xefe80000 +$filesize; "   \
 396        "erase 0xefe80000 +$filesize; " \
 397        "cp.b $loadaddr 0xefe80000 $filesize; " \
 398        "protect on 0xefe80000 +$filesize; "    \
 399        "cmp.b $loadaddr 0xefe80000 $filesize\0"        \
 400"ramdiskflash=tftpboot $loadaddr $ramdiskfile; "        \
 401        "protect off 0xeeb80000 +$filesize; "   \
 402        "erase 0xeeb80000 +$filesize; " \
 403        "cp.b $loadaddr 0xeeb80000 $filesize; " \
 404        "protect on 0xeeb80000 +$filesize; "    \
 405        "cmp.b $loadaddr 0xeeb80000 $filesize\0"        \
 406"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; "  \
 407        "protect off 0xefec0000 +$filesize; "   \
 408        "erase 0xefec0000 +$filesize; " \
 409        "cp.b $loadaddr 0xefec0000 $filesize; " \
 410        "protect on 0xefec0000 +$filesize; "    \
 411        "cmp.b $loadaddr 0xefec0000 $filesize\0"        \
 412"consoledev=ttyS0\0"    \
 413"ramdiskaddr=2000000\0" \
 414"ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 415"fdtaddr=1e00000\0"     \
 416"bdev=sda1\0"   \
 417"norbootaddr=ef080000\0"        \
 418"norfdtaddr=ef040000\0" \
 419"ramdisk_size=120000\0" \
 420"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
 421"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
 422
 423#define CONFIG_NFSBOOTCOMMAND   \
 424"setenv bootargs root=/dev/nfs rw "     \
 425"nfsroot=$serverip:$rootpath "  \
 426"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 427"console=$consoledev,$baudrate $othbootargs;" \
 428"tftp $loadaddr $bootfile&&"    \
 429"tftp $fdtaddr $fdtfile&&"      \
 430"bootm $loadaddr - $fdtaddr"
 431
 432#define CONFIG_HDBOOT   \
 433"setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 434"console=$consoledev,$baudrate $othbootargs;" \
 435"usb start;"    \
 436"ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
 437"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 438"bootm $loadaddr - $fdtaddr"
 439
 440#define CONFIG_USB_FAT_BOOT     \
 441"setenv bootargs root=/dev/ram rw "     \
 442"console=$consoledev,$baudrate $othbootargs " \
 443"ramdisk_size=$ramdisk_size;"   \
 444"usb start;"    \
 445"fatload usb 0:2 $loadaddr $bootfile;"  \
 446"fatload usb 0:2 $fdtaddr $fdtfile;"    \
 447"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 448"bootm $loadaddr $ramdiskaddr $fdtaddr"
 449
 450#define CONFIG_USB_EXT2_BOOT    \
 451"setenv bootargs root=/dev/ram rw "     \
 452"console=$consoledev,$baudrate $othbootargs " \
 453"ramdisk_size=$ramdisk_size;"   \
 454"usb start;"    \
 455"ext2load usb 0:4 $loadaddr $bootfile;" \
 456"ext2load usb 0:4 $fdtaddr $fdtfile;" \
 457"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
 458"bootm $loadaddr $ramdiskaddr $fdtaddr"
 459
 460#define CONFIG_NORBOOT  \
 461"setenv bootargs root=/dev/mtdblock3 rw "       \
 462"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 463"bootm $norbootaddr - $norfdtaddr"
 464
 465#define CONFIG_RAMBOOTCOMMAND_TFTP      \
 466"setenv bootargs root=/dev/ram rw "     \
 467"console=$consoledev,$baudrate $othbootargs " \
 468"ramdisk_size=$ramdisk_size;"   \
 469"tftp $ramdiskaddr $ramdiskfile;"       \
 470"tftp $loadaddr $bootfile;"     \
 471"tftp $fdtaddr $fdtfile;"       \
 472"bootm $loadaddr $ramdiskaddr $fdtaddr"
 473
 474#define CONFIG_RAMBOOTCOMMAND   \
 475"setenv bootargs root=/dev/ram rw "     \
 476"console=$consoledev,$baudrate $othbootargs " \
 477"ramdisk_size=$ramdisk_size;"   \
 478"bootm 0xefa80000 0xeeb80000 0xefe80000"
 479
 480#define CONFIG_BOOTCOMMAND      CONFIG_RAMBOOTCOMMAND
 481
 482#endif /* __CONFIG_H */
 483