LXR uboot/arch/arm/include/asm/arch-rockchip/pmu

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (c) 2015 Google, Inc
   4 *
   5 * Copyright 2014 Rockchip Inc.
   6 */
   7
   8#ifndef _ASM_ARCH_PMU_RK3288_H
   9#define _ASM_ARCH_PMU_RK3288_H
  10
  11struct rk3288_pmu {
  12        u32 wakeup_cfg[2];
  13        u32 pwrdn_con;
  14        u32 pwrdn_st;
  15
  16        u32 idle_req;
  17        u32 idle_st;
  18        u32 pwrmode_con;
  19        u32 pwr_state;
  20
  21        u32 osc_cnt;
  22        u32 pll_cnt;
  23        u32 stabl_cnt;
  24        u32 ddr0io_pwron_cnt;
  25
  26        u32 ddr1io_pwron_cnt;
  27        u32 core_pwrdn_cnt;
  28        u32 core_pwrup_cnt;
  29        u32 gpu_pwrdn_cnt;
  30
  31        u32 gpu_pwrup_cnt;
  32        u32 wakeup_rst_clr_cnt;
  33        u32 sft_con;
  34        u32 ddr_sref_st;
  35
  36        u32 int_con;
  37        u32 int_st;
  38        u32 boot_addr_sel;
  39        u32 grf_con;
  40
  41        u32 gpio_sr;
  42        u32 gpio0pull[3];
  43
  44        u32 gpio0drv[3];
  45        u32 gpio_op;
  46
  47        u32 gpio0_sel18;        /* 0x80 */
  48        u32 gpio0_iomux[4];     /* a, b, c, d */
  49        u32 sys_reg[4];
  50};
  51check_member(rk3288_pmu, sys_reg[3], 0x00a0);
  52
  53enum {
  54        PMU_GPIO0_A     = 0,
  55        PMU_GPIO0_B,
  56        PMU_GPIO0_C,
  57        PMU_GPIO0_D,
  58};
  59
  60/* PMU_GPIO0_B_IOMUX */
  61enum {
  62        GPIO0_B7_SHIFT          = 14,
  63        GPIO0_B7_MASK           = 1,
  64        GPIO0_B7_GPIOB7         = 0,
  65        GPIO0_B7_I2C0PMU_SDA,
  66
  67        GPIO0_B5_SHIFT          = 10,
  68        GPIO0_B5_MASK           = 1,
  69        GPIO0_B5_GPIOB5         = 0,
  70        GPIO0_B5_CLK_27M,
  71
  72        GPIO0_B2_SHIFT          = 4,
  73        GPIO0_B2_MASK           = 1,
  74        GPIO0_B2_GPIOB2         = 0,
  75        GPIO0_B2_TSADC_INT,
  76};
  77
  78/* PMU_GPIO0_C_IOMUX */
  79enum {
  80        GPIO0_C1_SHIFT          = 2,
  81        GPIO0_C1_MASK           = 3,
  82        GPIO0_C1_GPIOC1         = 0,
  83        GPIO0_C1_TEST_CLKOUT,
  84        GPIO0_C1_CLKT1_27M,
  85
  86        GPIO0_C0_SHIFT          = 0,
  87        GPIO0_C0_MASK           = 1,
  88        GPIO0_C0_GPIOC0         = 0,
  89        GPIO0_C0_I2C0PMU_SCL,
  90};
  91
  92#endif
  93