LXR uboot/arch/arm/include/asm/arch-rockchip/sdram

   1/* SPDX-License-Identifier:     GPL-2.0+ */
   2/*
   3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd
   4 */
   5
   6#ifndef _ASM_ARCH_SDRAM_PX30_H
   7#define _ASM_ARCH_SDRAM_PX30_H
   8#include <asm/arch-rockchip/sdram_common.h>
   9#include <asm/arch-rockchip/sdram_msch.h>
  10#include <asm/arch-rockchip/sdram_pctl_px30.h>
  11#include <asm/arch-rockchip/sdram_phy_px30.h>
  12#include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h>
  13
  14#define SR_IDLE                         93
  15#define PD_IDLE                         13
  16
  17/* PMUGRF */
  18#define PMUGRF_OS_REG0                  (0x200)
  19#define PMUGRF_OS_REG(n)                (PMUGRF_OS_REG0 + (n) * 4)
  20
  21/* DDR GRF */
  22#define DDR_GRF_CON(n)                  (0 + (n) * 4)
  23#define DDR_GRF_STATUS_BASE             (0X100)
  24#define DDR_GRF_STATUS(n)               (DDR_GRF_STATUS_BASE + (n) * 4)
  25#define DDR_GRF_LP_CON                  (0x20)
  26
  27#define SPLIT_MODE_32_L16_VALID         (0)
  28#define SPLIT_MODE_32_H16_VALID         (1)
  29#define SPLIT_MODE_16_L8_VALID          (2)
  30#define SPLIT_MODE_16_H8_VALID          (3)
  31
  32#define DDR_GRF_SPLIT_CON               (0x8)
  33#define SPLIT_MODE_MASK                 (0x3)
  34#define SPLIT_MODE_OFFSET               (9)
  35#define SPLIT_BYPASS_MASK               (1)
  36#define SPLIT_BYPASS_OFFSET             (8)
  37#define SPLIT_SIZE_MASK                 (0xff)
  38#define SPLIT_SIZE_OFFSET               (0)
  39
  40/* CRU define */
  41/* CRU_PLL_CON0 */
  42#define PB(n)                           ((0x1 << (15 + 16)) | ((n) << 15))
  43#define POSTDIV1(n)                     ((0x7 << (12 + 16)) | ((n) << 12))
  44#define FBDIV(n)                        ((0xFFF << 16) | (n))
  45
  46/* CRU_PLL_CON1 */
  47#define RSTMODE(n)                      ((0x1 << (15 + 16)) | ((n) << 15))
  48#define RST(n)                          ((0x1 << (14 + 16)) | ((n) << 14))
  49#define PD(n)                           ((0x1 << (13 + 16)) | ((n) << 13))
  50#define DSMPD(n)                        ((0x1 << (12 + 16)) | ((n) << 12))
  51#define LOCK(n)                         (((n) >> 10) & 0x1)
  52#define POSTDIV2(n)                     ((0x7 << (6 + 16)) | ((n) << 6))
  53#define REFDIV(n)                       ((0x3F << 16) | (n))
  54
  55/* CRU_MODE */
  56#define CLOCK_FROM_XIN_OSC              (0)
  57#define CLOCK_FROM_PLL                  (1)
  58#define CLOCK_FROM_RTC_32K              (2)
  59#define DPLL_MODE(n)                    ((0x3 << (4 + 16)) | ((n) << 4))
  60
  61/* CRU_SOFTRESET_CON1 */
  62#define upctl2_psrstn_req(n)            (((0x1 << 6) << 16) | ((n) << 6))
  63#define upctl2_asrstn_req(n)            (((0x1 << 5) << 16) | ((n) << 5))
  64#define upctl2_srstn_req(n)             (((0x1 << 4) << 16) | ((n) << 4))
  65
  66/* CRU_SOFTRESET_CON2 */
  67#define ddrphy_psrstn_req(n)            (((0x1 << 2) << 16) | ((n) << 2))
  68#define ddrphy_srstn_req(n)             (((0x1 << 0) << 16) | ((n) << 0))
  69
  70/* CRU register */
  71#define CRU_PLL_CON(pll_id, n)          ((pll_id)  * 0x20 + (n) * 4)
  72#define CRU_MODE                        (0xa0)
  73#define CRU_GLB_CNT_TH                  (0xb0)
  74#define CRU_CLKSEL_CON_BASE             0x100
  75#define CRU_CLKSELS_CON(i)              (CRU_CLKSEL_CON_BASE + ((i) * 4))
  76#define CRU_CLKGATE_CON_BASE            0x200
  77#define CRU_CLKGATE_CON(i)              (CRU_CLKGATE_CON_BASE + ((i) * 4))
  78#define CRU_CLKSFTRST_CON_BASE          0x300
  79#define CRU_CLKSFTRST_CON(i)            (CRU_CLKSFTRST_CON_BASE + ((i) * 4))
  80
  81struct px30_ddr_grf_regs {
  82        u32 ddr_grf_con[4];
  83        u32 reserved1[(0x20 - 0x10) / 4];
  84        u32 ddr_grf_lp_con;
  85        u32 reserved2[(0x100 - 0x24) / 4];
  86        u32 ddr_grf_status[11];
  87};
  88
  89struct msch_regs {
  90        u32 coreid;
  91        u32 revisionid;
  92        u32 deviceconf;
  93        u32 devicesize;
  94        u32 ddrtiminga0;
  95        u32 ddrtimingb0;
  96        u32 ddrtimingc0;
  97        u32 devtodev0;
  98        u32 reserved1[(0x110 - 0x20) / 4];
  99        u32 ddrmode;
 100        u32 ddr4timing;
 101        u32 reserved2[(0x1000 - 0x118) / 4];
 102        u32 agingx0;
 103        u32 reserved3[(0x1040 - 0x1004) / 4];
 104        u32 aging0;
 105        u32 aging1;
 106        u32 aging2;
 107        u32 aging3;
 108};
 109
 110struct sdram_msch_timings {
 111        union noc_ddrtiminga0 ddrtiminga0;
 112        union noc_ddrtimingb0 ddrtimingb0;
 113        union noc_ddrtimingc0 ddrtimingc0;
 114        union noc_devtodev0 devtodev0;
 115        union noc_ddrmode ddrmode;
 116        union noc_ddr4timing ddr4timing;
 117        u32 agingx0;
 118};
 119
 120struct px30_sdram_channel {
 121        struct sdram_cap_info cap_info;
 122        struct sdram_msch_timings noc_timings;
 123};
 124
 125struct px30_sdram_params {
 126        struct px30_sdram_channel ch;
 127        struct sdram_base_params base;
 128        struct ddr_pctl_regs pctl_regs;
 129        struct ddr_phy_regs phy_regs;
 130        struct ddr_phy_skew *skew;
 131};
 132
 133int sdram_init(void);
 134#endif
 135