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7#ifndef _ASM_ARCH_SDRAM_RK3328_H
8#define _ASM_ARCH_SDRAM_RK3328_H
9#include <asm/arch-rockchip/sdram_common.h>
10#include <asm/arch-rockchip/sdram_pctl_px30.h>
11#include <asm/arch-rockchip/sdram_phy_px30.h>
12#include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h>
13
14#define SR_IDLE 93
15#define PD_IDLE 13
16#define SDRAM_ADDR 0x00000000
17
18
19#define DDRCONF 0x8
20#define DDRTIMING 0xc
21#define DDRMODE 0x10
22#define READLATENCY 0x14
23#define AGING0 0x18
24#define AGING1 0x1c
25#define AGING2 0x20
26#define AGING3 0x24
27#define AGING4 0x28
28#define AGING5 0x2c
29#define ACTIVATE 0x38
30#define DEVTODEV 0x3c
31#define DDR4TIMING 0x40
32
33
34#define DDR_GRF_CON(n) (0 + (n) * 4)
35#define DDR_GRF_STATUS_BASE (0X100)
36#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
37
38
39#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | ((n) << 15))
40#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | ((n) << 14))
41#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | ((n) << 13))
42#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | ((n) << 12))
43#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | ((n) << 11))
44#define msch_srstn_req(n) (((0x1 << 9) << 16) | ((n) << 9))
45#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | ((n) << 8))
46#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | ((n) << 7))
47
48#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | ((n) << 9))
49
50
51#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
52#define CRU_MODE (0x80)
53#define CRU_GLB_CNT_TH (0x90)
54#define CRU_CLKSEL_CON_BASE 0x100
55#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4))
56#define CRU_CLKGATE_CON_BASE 0x200
57#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4))
58#define CRU_CLKSFTRST_CON_BASE 0x300
59#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4))
60
61
62#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15))
63#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12))
64#define FBDIV(n) ((0xFFF << 16) | (n))
65
66
67#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15))
68#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14))
69#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13))
70#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12))
71#define LOCK(n) (((n) >> 10) & 0x1)
72#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6))
73#define REFDIV(n) ((0x3F << 16) | (n))
74
75u16 ddr_cfg_2_rbc[] = {
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82
83 ((3 << 4) | (0 << 3) | (1 << 2) | 0),
84 ((3 << 4) | (0 << 3) | (1 << 2) | 1),
85 ((2 << 4) | (0 << 3) | (1 << 2) | 2),
86 ((3 << 4) | (0 << 3) | (1 << 2) | 2),
87 ((2 << 4) | (0 << 3) | (1 << 2) | 3),
88 ((3 << 4) | (1 << 3) | (1 << 2) | 0),
89 ((3 << 4) | (1 << 3) | (1 << 2) | 1),
90 ((2 << 4) | (1 << 3) | (1 << 2) | 2),
91 ((3 << 4) | (0 << 3) | (0 << 2) | 1),
92 ((2 << 4) | (0 << 3) | (1 << 2) | 1),
93};
94
95u16 ddr4_cfg_2_rbc[] = {
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102
103
104 ((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0),
105 ((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0),
106 ((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0),
107 ((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0),
108 ((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1),
109 ((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1),
110 ((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1),
111 ((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0),
112 ((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0),
113 ((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1),
114 ((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1),
115};
116
117u32 addrmap[21][9] = {
118
119 {22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606,
120 0x06060606, 0x00000f0f, 0x3f3f},
121 {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
122 0x07070707, 0x00000f0f, 0x3f3f},
123 {23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
124 0x0f080808, 0x00000f0f, 0x3f3f},
125 {24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
126 0x08080808, 0x00000f0f, 0x3f3f},
127 {24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909,
128 0x0f090909, 0x00000f0f, 0x3f3f},
129 {6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707,
130 0x07070707, 0x00000f0f, 0x3f3f},
131 {7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808,
132 0x08080808, 0x00000f0f, 0x3f3f},
133 {8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909,
134 0x0f090909, 0x00000f0f, 0x3f3f},
135 {22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606,
136 0x06060606, 0x00000f0f, 0x3f3f},
137 {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
138 0x0f070707, 0x00000f0f, 0x3f3f},
139
140 {24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
141 0x08080808, 0x00000f0f, 0x0801},
142 {23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
143 0x0f080808, 0x00000f0f, 0x0801},
144 {24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
145 0x07070707, 0x00000f07, 0x0700},
146 {23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
147 0x07070707, 0x00000f0f, 0x0700},
148 {24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
149 0x07070707, 0x00000f07, 0x3f01},
150 {23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
151 0x07070707, 0x00000f0f, 0x3f01},
152 {24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606,
153 0x06060606, 0x00000f06, 0x3f00},
154 {8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909,
155 0x0f090909, 0x00000f0f, 0x0801},
156 {7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808,
157 0x08080808, 0x00000f0f, 0x0700},
158 {7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
159 0x08080808, 0x00000f0f, 0x3f01},
160
161 {6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
162 0x07070707, 0x00000f07, 0x3f00}
163};
164
165struct rk3328_ddr_grf_regs {
166 u32 ddr_grf_con[4];
167 u32 reserved[(0x100 - 0x10) / 4];
168 u32 ddr_grf_status[11];
169};
170
171union noc_ddrtiming {
172 u32 d32;
173 struct {
174 unsigned acttoact:6;
175 unsigned rdtomiss:6;
176 unsigned wrtomiss:6;
177 unsigned burstlen:3;
178 unsigned rdtowr:5;
179 unsigned wrtord:5;
180 unsigned bwratio:1;
181 } b;
182};
183
184union noc_activate {
185 u32 d32;
186 struct {
187 unsigned rrd:4;
188 unsigned faw:6;
189 unsigned fawbank:1;
190 unsigned reserved1:21;
191 } b;
192};
193
194union noc_devtodev {
195 u32 d32;
196 struct {
197 unsigned busrdtord:2;
198 unsigned busrdtowr:2;
199 unsigned buswrtord:2;
200 unsigned reserved2:26;
201 } b;
202};
203
204union noc_ddr4timing {
205 u32 d32;
206 struct {
207 unsigned ccdl:3;
208 unsigned wrtordl:5;
209 unsigned rrdl:4;
210 unsigned reserved2:20;
211 } b;
212};
213
214union noc_ddrmode {
215 u32 d32;
216 struct {
217 unsigned autoprecharge:1;
218 unsigned bwratioextended:1;
219 unsigned reserved3:30;
220 } b;
221};
222
223struct msch_regs {
224 u32 coreid;
225 u32 revisionid;
226 u32 ddrconf;
227 u32 ddrtiming;
228 u32 ddrmode;
229 u32 readlatency;
230 u32 aging0;
231 u32 aging1;
232 u32 aging2;
233 u32 aging3;
234 u32 aging4;
235 u32 aging5;
236 u32 reserved[2];
237 u32 activate;
238 u32 devtodev;
239 u32 ddr4_timing;
240};
241
242struct sdram_msch_timings {
243 union noc_ddrtiming ddrtiming;
244 union noc_ddrmode ddrmode;
245 u32 readlatency;
246 union noc_activate activate;
247 union noc_devtodev devtodev;
248 union noc_ddr4timing ddr4timing;
249 u32 agingx0;
250};
251
252struct rk3328_sdram_channel {
253 struct sdram_cap_info cap_info;
254 struct sdram_msch_timings noc_timings;
255};
256
257struct rk3328_sdram_params {
258 struct rk3328_sdram_channel ch;
259 struct sdram_base_params base;
260 struct ddr_pctl_regs pctl_regs;
261 struct ddr_phy_regs phy_regs;
262 struct ddr_phy_skew skew;
263};
264
265#endif
266
