1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2012 Samsung Electronics 4 * 5 * Author: Donghwa Lee <dh09.lee@samsung.com> 6 */ 7 8#ifndef __ASM_ARM_ARCH_DP_H_ 9#define __ASM_ARM_ARCH_DP_H_ 10 11#ifndef __ASSEMBLY__ 12 13struct exynos_dp { 14 unsigned char res1[0x10]; 15 unsigned int tx_version; 16 unsigned int tx_sw_reset; 17 unsigned int func_en1; 18 unsigned int func_en2; 19 unsigned int video_ctl1; 20 unsigned int video_ctl2; 21 unsigned int video_ctl3; 22 unsigned int video_ctl4; 23 unsigned int color_blue_cb; 24 unsigned int color_green_y; 25 unsigned int color_red_cr; 26 unsigned int video_ctl8; 27 unsigned char res2[0x4]; 28 unsigned int video_ctl10; 29 unsigned int total_ln_cfg_l; 30 unsigned int total_ln_cfg_h; 31 unsigned int active_ln_cfg_l; 32 unsigned int active_ln_cfg_h; 33 unsigned int vfp_cfg; 34 unsigned int vsw_cfg; 35 unsigned int vbp_cfg; 36 unsigned int total_pix_cfg_l; 37 unsigned int total_pix_cfg_h; 38 unsigned int active_pix_cfg_l; 39 unsigned int active_pix_cfg_h; 40 unsigned int hfp_cfg_l; 41 unsigned int hfp_cfg_h; 42 unsigned int hsw_cfg_l; 43 unsigned int hsw_cfg_h; 44 unsigned int hbp_cfg_l; 45 unsigned int hbp_cfg_h; 46 unsigned int video_status; 47 unsigned int total_ln_sta_l; 48 unsigned int total_ln_sta_h; 49 unsigned int active_ln_sta_l; 50 unsigned int active_ln_sta_h; 51 52 unsigned int vfp_sta; 53 unsigned int vsw_sta; 54 unsigned int vbp_sta; 55 56 unsigned int total_pix_sta_l; 57 unsigned int total_pix_sta_h; 58 unsigned int active_pix_sta_l; 59 unsigned int active_pix_sta_h; 60 61 unsigned int hfp_sta_l; 62 unsigned int hfp_sta_h; 63 unsigned int hsw_sta_l; 64 unsigned int hsw_sta_h; 65 unsigned int hbp_sta_l; 66 unsigned int hbp_sta_h; 67 68 unsigned char res3[0x288]; 69 70 unsigned int lane_map; 71 unsigned char res4[0x10]; 72 unsigned int analog_ctl1; 73 unsigned int analog_ctl2; 74 unsigned int analog_ctl3; 75 76 unsigned int pll_filter_ctl1; 77 unsigned int amp_tuning_ctl; 78 unsigned char res5[0xc]; 79 80 unsigned int aux_hw_retry_ctl; 81 unsigned char res6[0x2c]; 82 unsigned int int_state; 83 unsigned int common_int_sta1; 84 unsigned int common_int_sta2; 85 unsigned int common_int_sta3; 86 unsigned int common_int_sta4; 87 unsigned char res7[0x8]; 88 89 unsigned int int_sta; 90 unsigned char res8[0x1c]; 91 unsigned int int_ctl; 92 unsigned char res9[0x200]; 93 unsigned int sys_ctl1; 94 unsigned int sys_ctl2; 95 unsigned int sys_ctl3; 96 unsigned int sys_ctl4; 97 unsigned int vid_ctl; 98 unsigned char res10[0x2c]; 99 unsigned int pkt_send_ctl; 100 unsigned char res[0x4]; 101 unsigned int hdcp_ctl; 102 unsigned char res11[0x34]; 103 unsigned int link_bw_set; 104 105 unsigned int lane_count_set; 106 unsigned int training_ptn_set; 107 unsigned int ln0_link_training_ctl; 108 unsigned int ln1_link_training_ctl; 109 unsigned int ln2_link_training_ctl; 110 unsigned int ln3_link_training_ctl; 111 unsigned int dn_spread_ctl; 112 unsigned int hw_link_training_ctl; 113 unsigned char res12[0x1c]; 114 115 unsigned int debug_ctl; 116 unsigned int hpd_deglitch_l; 117 unsigned int hpd_deglitch_h; 118 119 unsigned char res13[0x14]; 120 unsigned int link_debug_ctl; 121 122 unsigned char res14[0x1c]; 123 124 unsigned int m_vid0; 125 unsigned int m_vid1; 126 unsigned int m_vid2; 127 unsigned int n_vid0; 128 unsigned int n_vid1; 129 unsigned int n_vid2; 130 unsigned int m_vid_mon; 131 unsigned int pll_ctl; 132 unsigned int phy_pd; 133 unsigned int phy_test; 134 unsigned char res15[0x8]; 135 136 unsigned int video_fifo_thrd; 137 unsigned char res16[0x8]; 138 unsigned int audio_margin; 139 140 unsigned int dn_spread_ctl1; 141 unsigned int dn_spread_ctl2; 142 unsigned char res17[0x18]; 143 unsigned int m_cal_ctl; 144 unsigned int m_vid_gen_filter_th; 145 unsigned char res18[0x10]; 146 unsigned int m_aud_gen_filter_th; 147 unsigned char res50[0x4]; 148 149 unsigned int aux_ch_sta; 150 unsigned int aux_err_num; 151 unsigned int aux_ch_defer_ctl; 152 unsigned int aux_rx_comm; 153 unsigned int buffer_data_ctl; 154 155 unsigned int aux_ch_ctl1; 156 unsigned int aux_addr_7_0; 157 unsigned int aux_addr_15_8; 158 unsigned int aux_addr_19_16; 159 unsigned int aux_ch_ctl2; 160 unsigned char res19[0x18]; 161 unsigned int buf_data0; 162 unsigned char res20[0x3c]; 163 164 unsigned int soc_general_ctl; 165 unsigned char res21[0x8c]; 166 unsigned int crc_con; 167 unsigned int crc_result; 168 unsigned char res22[0x8]; 169 170 unsigned int common_int_mask1; 171 unsigned int common_int_mask2; 172 unsigned int common_int_mask3; 173 unsigned int common_int_mask4; 174 unsigned int int_sta_mask1; 175 unsigned int int_sta_mask2; 176 unsigned int int_sta_mask3; 177 unsigned int int_sta_mask4; 178 unsigned int int_sta_mask; 179 unsigned int crc_result2; 180 unsigned int scrambler_reset_cnt; 181 182 unsigned int pn_inv; 183 unsigned int psr_config; 184 unsigned int psr_command0; 185 unsigned int psr_command1; 186 unsigned int psr_crc_mon0; 187 unsigned int psr_crc_mon1; 188 189 unsigned char res24[0x30]; 190 unsigned int phy_bist_ctrl; 191 unsigned char res25[0xc]; 192 unsigned int phy_ctrl; 193 unsigned char res26[0x1c]; 194 unsigned int test_pattern_gen_en; 195 unsigned int test_pattern_gen_ctrl; 196}; 197 198#endif /* __ASSEMBLY__ */ 199 200/* For DP VIDEO CTL 1 */ 201#define VIDEO_EN_MASK (0x01 << 7) 202#define VIDEO_MUTE_MASK (0x01 << 6) 203 204/* For DP VIDEO CTL 4 */ 205#define VIDEO_BIST_MASK (0x1 << 3) 206 207/* EXYNOS_DP_ANALOG_CTL_1 */ 208#define SEL_BG_NEW_BANDGAP (0x0 << 6) 209#define SEL_BG_INTERNAL_RESISTOR (0x1 << 6) 210#define TX_TERMINAL_CTRL_73_OHM (0x0 << 4) 211#define TX_TERMINAL_CTRL_61_OHM (0x1 << 4) 212#define TX_TERMINAL_CTRL_50_OHM (0x2 << 4) 213#define TX_TERMINAL_CTRL_45_OHM (0x3 << 4) 214#define SWING_A_30PER_G_INCREASE (0x1 << 3) 215#define SWING_A_30PER_G_NORMAL (0x0 << 3) 216 217/* EXYNOS_DP_ANALOG_CTL_2 */ 218#define CPREG_BLEED (0x1 << 4) 219#define SEL_24M (0x1 << 3) 220#define TX_DVDD_BIT_1_0000V (0x3 << 0) 221#define TX_DVDD_BIT_1_0625V (0x4 << 0) 222#define TX_DVDD_BIT_1_1250V (0x5 << 0) 223 224/* EXYNOS_DP_ANALOG_CTL_3 */ 225#define DRIVE_DVDD_BIT_1_0000V (0x3 << 5) 226#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 227#define DRIVE_DVDD_BIT_1_1250V (0x5 << 5) 228#define SEL_CURRENT_DEFAULT (0x0 << 3) 229#define VCO_BIT_000_MICRO (0x0 << 0) 230#define VCO_BIT_200_MICRO (0x1 << 0) 231#define VCO_BIT_300_MICRO (0x2 << 0) 232#define VCO_BIT_400_MICRO (0x3 << 0) 233#define VCO_BIT_500_MICRO (0x4 << 0) 234#define VCO_BIT_600_MICRO (0x5 << 0) 235#define VCO_BIT_700_MICRO (0x6 << 0) 236#define VCO_BIT_900_MICRO (0x7 << 0) 237 238/* EXYNOS_DP_PLL_FILTER_CTL_1 */ 239#define PD_RING_OSC (0x1 << 6) 240#define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4) 241#define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4) 242#define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4) 243#define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4) 244#define TX_CUR1_1X (0x0 << 2) 245#define TX_CUR1_2X (0x1 << 2) 246#define TX_CUR1_3X (0x2 << 2) 247#define TX_CUR_1_MA (0x0 << 0) 248#define TX_CUR_2_MA (0x1 << 0) 249#define TX_CUR_3_MA (0x2 << 0) 250#define TX_CUR_4_MA (0x3 << 0) 251 252/* EXYNOS_DP_PLL_FILTER_CTL_2 */ 253#define CH3_AMP_0_MV (0x3 << 12) 254#define CH2_AMP_0_MV (0x3 << 8) 255#define CH1_AMP_0_MV (0x3 << 4) 256#define CH0_AMP_0_MV (0x3 << 0) 257 258/* EXYNOS_DP_PLL_CTL */ 259#define DP_PLL_PD (0x1 << 7) 260#define DP_PLL_RESET (0x1 << 6) 261#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 262#define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 263#define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 264 265/* EXYNOS_DP_INT_CTL */ 266#define SOFT_INT_CTRL (0x1 << 2) 267#define INT_POL (0x1 << 0) 268 269/* DP TX SW RESET */ 270#define RESET_DP_TX (0x01 << 0) 271 272/* DP FUNC_EN_1 */ 273#define MASTER_VID_FUNC_EN_N (0x1 << 7) 274#define SLAVE_VID_FUNC_EN_N (0x1 << 5) 275#define AUD_FIFO_FUNC_EN_N (0x1 << 4) 276#define AUD_FUNC_EN_N (0x1 << 3) 277#define HDCP_FUNC_EN_N (0x1 << 2) 278#define CRC_FUNC_EN_N (0x1 << 1) 279#define SW_FUNC_EN_N (0x1 << 0) 280 281/* DP FUNC_EN_2 */ 282#define SSC_FUNC_EN_N (0x1 << 7) 283#define AUX_FUNC_EN_N (0x1 << 2) 284#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 285#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 286 287/* EXYNOS_DP_PHY_PD */ 288#define PHY_PD (0x1 << 5) 289#define AUX_PD (0x1 << 4) 290#define CH3_PD (0x1 << 3) 291#define CH2_PD (0x1 << 2) 292#define CH1_PD (0x1 << 1) 293#define CH0_PD (0x1 << 0) 294 295/* EXYNOS_DP_COMMON_INT_STA_1 */ 296#define VSYNC_DET (0x1 << 7) 297#define PLL_LOCK_CHG (0x1 << 6) 298#define SPDIF_ERR (0x1 << 5) 299#define SPDIF_UNSTBL (0x1 << 4) 300#define VID_FORMAT_CHG (0x1 << 3) 301#define AUD_CLK_CHG (0x1 << 2) 302#define VID_CLK_CHG (0x1 << 1) 303#define SW_INT (0x1 << 0) 304 305/* EXYNOS_DP_DEBUG_CTL */ 306#define PLL_LOCK (0x1 << 4) 307#define F_PLL_LOCK (0x1 << 3) 308#define PLL_LOCK_CTRL (0x1 << 2) 309 310/* EXYNOS_DP_FUNC_EN_2 */ 311#define SSC_FUNC_EN_N (0x1 << 7) 312#define AUX_FUNC_EN_N (0x1 << 2) 313#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 314#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 315 316/* EXYNOS_DP_COMMON_INT_STA_4 */ 317#define PSR_ACTIVE (0x1 << 7) 318#define PSR_INACTIVE (0x1 << 6) 319#define SPDIF_BI_PHASE_ERR (0x1 << 5) 320#define HOTPLUG_CHG (0x1 << 2) 321#define HPD_LOST (0x1 << 1) 322#define PLUG (0x1 << 0) 323 324/* EXYNOS_DP_INT_STA */ 325#define INT_HPD (0x1 << 6) 326#define HW_TRAINING_FINISH (0x1 << 5) 327#define RPLY_RECEIV (0x1 << 1) 328#define AUX_ERR (0x1 << 0) 329 330/* EXYNOS_DP_SYS_CTL_3 */ 331#define HPD_STATUS (0x1 << 6) 332#define F_HPD (0x1 << 5) 333#define HPD_CTRL (0x1 << 4) 334#define HDCP_RDY (0x1 << 3) 335#define STRM_VALID (0x1 << 2) 336#define F_VALID (0x1 << 1) 337#define VALID_CTRL (0x1 << 0) 338 339/* EXYNOS_DP_AUX_HW_RETRY_CTL */ 340#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 341#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 342#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 343#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 344#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 345#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 346#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 347 348/* EXYNOS_DP_AUX_CH_DEFER_CTL */ 349#define DEFER_CTRL_EN (0x1 << 7) 350#define DEFER_COUNT(x) (((x) & 0x7f) << 0) 351 352#define COMMON_INT_MASK_1 (0) 353#define COMMON_INT_MASK_2 (0) 354#define COMMON_INT_MASK_3 (0) 355#define COMMON_INT_MASK_4 (0) 356#define INT_STA_MASK (0) 357 358/* EXYNOS_DP_BUFFER_DATA_CTL */ 359#define BUF_CLR (0x1 << 7) 360#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 361 362/* EXYNOS_DP_AUX_ADDR_7_0 */ 363#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 364 365/* EXYNOS_DP_AUX_ADDR_15_8 */ 366#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 367 368/* EXYNOS_DP_AUX_ADDR_19_16 */ 369#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 370 371/* EXYNOS_DP_AUX_CH_CTL_1 */ 372#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 373#define AUX_TX_COMM_MASK (0xf << 0) 374#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 375#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 376#define AUX_TX_COMM_MOT (0x1 << 2) 377#define AUX_TX_COMM_WRITE (0x0 << 0) 378#define AUX_TX_COMM_READ (0x1 << 0) 379 380/* EXYNOS_DP_AUX_CH_CTL_2 */ 381#define ADDR_ONLY (0x1 << 1) 382#define AUX_EN (0x1 << 0) 383 384/* EXYNOS_DP_AUX_CH_STA */ 385#define AUX_BUSY (0x1 << 4) 386#define AUX_STATUS_MASK (0xf << 0) 387 388/* EXYNOS_DP_AUX_RX_COMM */ 389#define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 390#define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 391 392/* EXYNOS_DP_PHY_TEST */ 393#define MACRO_RST (0x1 << 5) 394#define CH1_TEST (0x1 << 1) 395#define CH0_TEST (0x1 << 0) 396 397/* EXYNOS_DP_TRAINING_PTN_SET */ 398#define SCRAMBLER_TYPE (0x1 << 9) 399#define HW_LINK_TRAINING_PATTERN (0x1 << 8) 400#define SCRAMBLING_DISABLE (0x1 << 5) 401#define SCRAMBLING_ENABLE (0x0 << 5) 402#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 403#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 404#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 405#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 406#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 407#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 408#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 409#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 410 411/* EXYNOS_DP_TOTAL_LINE_CFG */ 412#define TOTAL_LINE_CFG_L(x) ((x) & 0xff) 413#define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff) 414#define ACTIVE_LINE_CFG_L(x) ((x) & 0xff) 415#define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff) 416#define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff) 417#define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff) 418#define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff) 419#define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff) 420 421#define H_F_PORCH_CFG_L(x) ((x) & 0xff) 422#define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) 423#define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff) 424#define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) 425#define H_B_PORCH_CFG_L(x) ((x) & 0xff) 426#define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) 427 428/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */ 429#define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5) 430#define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3) 431#define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3) 432#define PRE_EMPHASIS_SET_0_MASK (0x3 << 3) 433#define PRE_EMPHASIS_SET_0_SHIFT (3) 434#define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3) 435#define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3) 436#define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3) 437#define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3) 438#define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2) 439#define DRIVE_CURRENT_SET_0_MASK (0x3 << 0) 440#define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0) 441#define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3) 442#define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0) 443#define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0) 444#define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0) 445#define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0) 446 447/* EXYNOS_DP_LN1_LINK_TRAINING_CTL */ 448#define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5) 449#define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3) 450#define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3) 451#define PRE_EMPHASIS_SET_1_MASK (0x3 << 3) 452#define PRE_EMPHASIS_SET_1_SHIFT (3) 453#define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3) 454#define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3) 455#define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3) 456#define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3) 457#define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2) 458#define DRIVE_CURRENT_SET_1_MASK (0x3 << 0) 459#define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0) 460#define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3) 461#define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0) 462#define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0) 463#define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0) 464#define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0) 465 466/* EXYNOS_DP_LN2_LINK_TRAINING_CTL */ 467#define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5) 468#define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3) 469#define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3) 470#define PRE_EMPHASIS_SET_2_MASK (0x3 << 3) 471#define PRE_EMPHASIS_SET_2_SHIFT (3) 472#define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3) 473#define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3) 474#define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3) 475#define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3) 476#define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2) 477#define DRIVE_CURRENT_SET_2_MASK (0x3 << 0) 478#define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0) 479#define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3) 480#define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0) 481#define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0) 482#define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0) 483#define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0) 484 485/* EXYNOS_DP_LN3_LINK_TRAINING_CTL */ 486#define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5) 487#define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3) 488#define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3) 489#define PRE_EMPHASIS_SET_3_MASK (0x3 << 3) 490#define PRE_EMPHASIS_SET_3_SHIFT (3) 491#define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3) 492#define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3) 493#define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3) 494#define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3) 495#define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2) 496#define DRIVE_CURRENT_SET_3_MASK (0x3 << 0) 497#define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0) 498#define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3) 499#define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0) 500#define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0) 501#define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0) 502#define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0) 503 504/* EXYNOS_DP_VIDEO_CTL_10 */ 505#define FORMAT_SEL (0x1 << 4) 506#define INTERACE_SCAN_CFG (0x1 << 2) 507#define INTERACE_SCAN_CFG_SHIFT (2) 508#define VSYNC_POLARITY_CFG (0x1 << 1) 509#define V_S_POLARITY_CFG_SHIFT (1) 510#define HSYNC_POLARITY_CFG (0x1 << 0) 511#define H_S_POLARITY_CFG_SHIFT (0) 512 513/* EXYNOS_DP_SOC_GENERAL_CTL */ 514#define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 515#define AUDIO_MODE_MASTER_MODE (0x0 << 8) 516#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 517#define VIDEO_MASTER_CLK_SEL (0x1 << 2) 518#define VIDEO_MASTER_MODE_EN (0x1 << 1) 519#define VIDEO_MODE_MASK (0x1 << 0) 520#define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 521#define VIDEO_MODE_MASTER_MODE (0x0 << 0) 522 523/* EXYNOS_DP_VIDEO_CTL_1 */ 524#define VIDEO_EN (0x1 << 7) 525#define HDCP_VIDEO_MUTE (0x1 << 6) 526 527/* EXYNOS_DP_VIDEO_CTL_2 */ 528#define IN_D_RANGE_MASK (0x1 << 7) 529#define IN_D_RANGE_SHIFT (7) 530#define IN_D_RANGE_CEA (0x1 << 7) 531#define IN_D_RANGE_VESA (0x0 << 7) 532#define IN_BPC_MASK (0x7 << 4) 533#define IN_BPC_SHIFT (4) 534#define IN_BPC_12_BITS (0x3 << 4) 535#define IN_BPC_10_BITS (0x2 << 4) 536#define IN_BPC_8_BITS (0x1 << 4) 537#define IN_BPC_6_BITS (0x0 << 4) 538#define IN_COLOR_F_MASK (0x3 << 0) 539#define IN_COLOR_F_SHIFT (0) 540#define IN_COLOR_F_YCBCR444 (0x2 << 0) 541#define IN_COLOR_F_YCBCR422 (0x1 << 0) 542#define IN_COLOR_F_RGB (0x0 << 0) 543 544/* EXYNOS_DP_VIDEO_CTL_3 */ 545#define IN_YC_COEFFI_MASK (0x1 << 7) 546#define IN_YC_COEFFI_SHIFT (7) 547#define IN_YC_COEFFI_ITU709 (0x1 << 7) 548#define IN_YC_COEFFI_ITU601 (0x0 << 7) 549#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 550#define VID_CHK_UPDATE_TYPE_SHIFT (4) 551#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 552#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 553 554/* EXYNOS_DP_TEST_PATTERN_GEN_EN */ 555#define TEST_PATTERN_GEN_EN (0x1 << 0) 556#define TEST_PATTERN_GEN_DIS (0x0 << 0) 557 558/* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */ 559#define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0) 560#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0) 561#define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0) 562 563/* EXYNOS_DP_VIDEO_CTL_4 */ 564#define BIST_EN (0x1 << 3) 565#define BIST_WIDTH_MASK (0x1 << 2) 566#define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2) 567#define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2) 568#define BIST_TYPE_MASK (0x3 << 0) 569#define BIST_TYPE_COLOR_BAR (0x0 << 0) 570#define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0) 571#define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0) 572 573/* EXYNOS_DP_SYS_CTL_1 */ 574#define DET_STA (0x1 << 2) 575#define FORCE_DET (0x1 << 1) 576#define DET_CTRL (0x1 << 0) 577 578/* EXYNOS_DP_SYS_CTL_2 */ 579#define CHA_CRI(x) (((x) & 0xf) << 4) 580#define CHA_STA (0x1 << 2) 581#define FORCE_CHA (0x1 << 1) 582#define CHA_CTRL (0x1 << 0) 583 584/* EXYNOS_DP_SYS_CTL_3 */ 585#define HPD_STATUS (0x1 << 6) 586#define F_HPD (0x1 << 5) 587#define HPD_CTRL (0x1 << 4) 588#define HDCP_RDY (0x1 << 3) 589#define STRM_VALID (0x1 << 2) 590#define F_VALID (0x1 << 1) 591#define VALID_CTRL (0x1 << 0) 592 593/* EXYNOS_DP_SYS_CTL_4 */ 594#define FIX_M_AUD (0x1 << 4) 595#define ENHANCED (0x1 << 3) 596#define FIX_M_VID (0x1 << 2) 597#define M_VID_UPDATE_CTRL (0x3 << 0) 598 599/* EXYNOS_M_VID_X */ 600#define M_VID0_CFG(x) ((x) & 0xff) 601#define M_VID1_CFG(x) (((x) >> 8) & 0xff) 602#define M_VID2_CFG(x) (((x) >> 16) & 0xff) 603 604/* EXYNOS_M_VID_X */ 605#define N_VID0_CFG(x) ((x) & 0xff) 606#define N_VID1_CFG(x) (((x) >> 8) & 0xff) 607#define N_VID2_CFG(x) (((x) >> 16) & 0xff) 608 609/* DPCD_TRAINING_PATTERN_SET */ 610#define DPCD_SCRAMBLING_DISABLED (0x1 << 5) 611#define DPCD_SCRAMBLING_ENABLED (0x0 << 5) 612#define DPCD_TRAINING_PATTERN_2 (0x2 << 0) 613#define DPCD_TRAINING_PATTERN_1 (0x1 << 0) 614#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0) 615 616/* Definition for DPCD Register */ 617#define DPCD_DPCD_REV (0x0000) 618#define DPCD_MAX_LINK_RATE (0x0001) 619#define DPCD_MAX_LANE_COUNT (0x0002) 620#define DPCD_LINK_BW_SET (0x0100) 621#define DPCD_LANE_COUNT_SET (0x0101) 622#define DPCD_TRAINING_PATTERN_SET (0x0102) 623#define DPCD_TRAINING_LANE0_SET (0x0103) 624#define DPCD_LANE0_1_STATUS (0x0202) 625#define DPCD_LN_ALIGN_UPDATED (0x0204) 626#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206) 627#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207) 628#define DPCD_TEST_REQUEST (0x0218) 629#define DPCD_TEST_RESPONSE (0x0260) 630#define DPCD_TEST_EDID_CHECKSUM (0x0261) 631#define DPCD_SINK_POWER_STATE (0x0600) 632 633/* DPCD_TEST_REQUEST */ 634#define DPCD_TEST_EDID_READ (0x1 << 2) 635 636/* DPCD_TEST_RESPONSE */ 637#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2) 638 639/* DPCD_SINK_POWER_STATE */ 640#define DPCD_SET_POWER_STATE_D0 (0x1 << 0) 641#define DPCD_SET_POWER_STATE_D4 (0x2 << 0) 642 643/* I2C EDID Chip ID, Slave Address */ 644#define I2C_EDID_DEVICE_ADDR (0x50) 645#define I2C_E_EDID_DEVICE_ADDR (0x30) 646#define EDID_BLOCK_LENGTH (0x80) 647#define EDID_HEADER_PATTERN (0x00) 648#define EDID_EXTENSION_FLAG (0x7e) 649#define EDID_CHECKSUM (0x7f) 650 651/* DPCD_LANE0_1_STATUS */ 652#define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6) 653#define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5) 654#define DPCD_LANE1_CR_DONE (0x1 << 4) 655#define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2) 656#define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1) 657#define DPCD_LANE0_CR_DONE (0x1 << 0) 658 659/* DPCD_ADJUST_REQUEST_LANE0_1 */ 660#define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6) 661#define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3) 662#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6) 663#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6) 664#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6) 665#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6) 666#define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4) 667#define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3) 668#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4) 669#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4) 670#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4) 671#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4) 672#define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2) 673#define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3) 674#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2) 675#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2) 676#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2) 677#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2) 678#define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0) 679#define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3) 680#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0) 681#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0) 682#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0) 683#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0) 684 685/* DPCD_ADJUST_REQUEST_LANE2_3 */ 686#define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6) 687#define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3) 688#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6) 689#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6) 690#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6) 691#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6) 692#define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4) 693#define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3) 694#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4) 695#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4) 696#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4) 697#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4) 698#define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2) 699#define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3) 700#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2) 701#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2) 702#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2) 703#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2) 704#define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0) 705#define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3) 706#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0) 707#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0) 708#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0) 709#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0) 710 711/* DPCD_LANE_COUNT_SET */ 712#define DPCD_ENHANCED_FRAME_EN (0x1 << 7) 713#define DPCD_LN_COUNT_SET(x) ((x) & 0x1f) 714 715/* DPCD_LANE_ALIGN__STATUS_UPDATED */ 716#define DPCD_LINK_STATUS_UPDATED (0x1 << 7) 717#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6) 718#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0) 719 720/* DPCD_TRAINING_LANE0_SET */ 721#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3) 722#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3) 723#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3) 724#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3) 725#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0) 726#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0) 727#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0) 728#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0) 729 730#define DPCD_REQ_ADJ_SWING (0x00) 731#define DPCD_REQ_ADJ_EMPHASIS (0x01) 732 733#define DP_LANE_STAT_CR_DONE (0x01 << 0) 734#define DP_LANE_STAT_CE_DONE (0x01 << 1) 735#define DP_LANE_STAT_SYM_LOCK (0x01 << 2) 736 737#endif 738