LXR uboot/arch/arm/mach-socfpga/clock_manager

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
   4 */
   5
   6#include <common.h>
   7#include <time.h>
   8#include <asm/io.h>
   9#include <dm.h>
  10#include <asm/arch/clock_manager.h>
  11#include <wait_bit.h>
  12
  13static const struct socfpga_clock_manager *clock_manager_base =
  14        (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
  15
  16/*
  17 * function to write the bypass register which requires a poll of the
  18 * busy bit
  19 */
  20static void cm_write_bypass(u32 val)
  21{
  22        writel(val, &clock_manager_base->bypass);
  23        cm_wait_for_fsm();
  24}
  25
  26/* function to write the ctrl register which requires a poll of the busy bit */
  27static void cm_write_ctrl(u32 val)
  28{
  29        writel(val, &clock_manager_base->ctrl);
  30        cm_wait_for_fsm();
  31}
  32
  33/* function to write a clock register that has phase information */
  34static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)
  35{
  36        int ret;
  37
  38        /* poll until phase is zero */
  39        ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
  40        if (ret)
  41                return ret;
  42
  43        writel(value, reg_address);
  44
  45        return wait_for_bit_le32(reg_address, mask, false, 20000, false);
  46}
  47
  48/*
  49 * Setup clocks while making no assumptions about previous state of the clocks.
  50 *
  51 * Start by being paranoid and gate all sw managed clocks
  52 * Put all plls in bypass
  53 * Put all plls VCO registers back to reset value (bandgap power down).
  54 * Put peripheral and main pll src to reset value to avoid glitch.
  55 * Delay 5 us.
  56 * Deassert bandgap power down and set numerator and denominator
  57 * Start 7 us timer.
  58 * set internal dividers
  59 * Wait for 7 us timer.
  60 * Enable plls
  61 * Set external dividers while plls are locking
  62 * Wait for pll lock
  63 * Assert/deassert outreset all.
  64 * Take all pll's out of bypass
  65 * Clear safe mode
  66 * set source main and peripheral clocks
  67 * Ungate clocks
  68 */
  69
  70int cm_basic_init(const struct cm_config * const cfg)
  71{
  72        unsigned long end;
  73        int ret;
  74
  75        /* Start by being paranoid and gate all sw managed clocks */
  76
  77        /*
  78         * We need to disable nandclk
  79         * and then do another apb access before disabling
  80         * gatting off the rest of the periperal clocks.
  81         */
  82        writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
  83                readl(&clock_manager_base->per_pll.en),
  84                &clock_manager_base->per_pll.en);
  85
  86        /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
  87        writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
  88                CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
  89                CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
  90                CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
  91                CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
  92                CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
  93                &clock_manager_base->main_pll.en);
  94
  95        writel(0, &clock_manager_base->sdr_pll.en);
  96
  97        /* now we can gate off the rest of the peripheral clocks */
  98        writel(0, &clock_manager_base->per_pll.en);
  99
 100        /* Put all plls in bypass */
 101        cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
 102                        CLKMGR_BYPASS_MAINPLL);
 103
 104        /* Put all plls VCO registers back to reset value. */
 105        writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
 106               ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
 107               &clock_manager_base->main_pll.vco);
 108        writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
 109               ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
 110               &clock_manager_base->per_pll.vco);
 111        writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
 112               ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
 113               &clock_manager_base->sdr_pll.vco);
 114
 115        /*
 116         * The clocks to the flash devices and the L4_MAIN clocks can
 117         * glitch when coming out of safe mode if their source values
 118         * are different from their reset value.  So the trick it to
 119         * put them back to their reset state, and change input
 120         * after exiting safe mode but before ungating the clocks.
 121         */
 122        writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
 123               &clock_manager_base->per_pll.src);
 124        writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
 125               &clock_manager_base->main_pll.l4src);
 126
 127        /* read back for the required 5 us delay. */
 128        readl(&clock_manager_base->main_pll.vco);
 129        readl(&clock_manager_base->per_pll.vco);
 130        readl(&clock_manager_base->sdr_pll.vco);
 131
 132
 133        /*
 134         * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
 135         * with numerator and denominator.
 136         */
 137        writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
 138        writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
 139        writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
 140
 141        /*
 142         * Time starts here. Must wait 7 us from
 143         * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
 144         */
 145        end = timer_get_us() + 7;
 146
 147        /* main mpu */
 148        writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
 149
 150        /* altera group mpuclk */
 151        writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
 152
 153        /* main main clock */
 154        writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
 155
 156        /* main for dbg */
 157        writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
 158
 159        /* main for cfgs2fuser0clk */
 160        writel(cfg->cfg2fuser0clk,
 161               &clock_manager_base->main_pll.cfgs2fuser0clk);
 162
 163        /* Peri emac0 50 MHz default to RMII */
 164        writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
 165
 166        /* Peri emac1 50 MHz default to RMII */
 167        writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
 168
 169        /* Peri QSPI */
 170        writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
 171
 172        writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
 173
 174        /* Peri pernandsdmmcclk */
 175        writel(cfg->mainnandsdmmcclk,
 176               &clock_manager_base->main_pll.mainnandsdmmcclk);
 177
 178        writel(cfg->pernandsdmmcclk,
 179               &clock_manager_base->per_pll.pernandsdmmcclk);
 180
 181        /* Peri perbaseclk */
 182        writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
 183
 184        /* Peri s2fuser1clk */
 185        writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
 186
 187        /* 7 us must have elapsed before we can enable the VCO */
 188        while (timer_get_us() < end)
 189                ;
 190
 191        /* Enable vco */
 192        /* main pll vco */
 193        writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 194               &clock_manager_base->main_pll.vco);
 195
 196        /* periferal pll */
 197        writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 198               &clock_manager_base->per_pll.vco);
 199
 200        /* sdram pll vco */
 201        writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 202               &clock_manager_base->sdr_pll.vco);
 203
 204        /* L3 MP and L3 SP */
 205        writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
 206
 207        writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
 208
 209        writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
 210
 211        /* L4 MP, L4 SP, can0, and can1 */
 212        writel(cfg->perdiv, &clock_manager_base->per_pll.div);
 213
 214        writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
 215
 216        cm_wait_for_lock(LOCKED_MASK);
 217
 218        /* write the sdram clock counters before toggling outreset all */
 219        writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
 220               &clock_manager_base->sdr_pll.ddrdqsclk);
 221
 222        writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
 223               &clock_manager_base->sdr_pll.ddr2xdqsclk);
 224
 225        writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
 226               &clock_manager_base->sdr_pll.ddrdqclk);
 227
 228        writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
 229               &clock_manager_base->sdr_pll.s2fuser2clk);
 230
 231        /*
 232         * after locking, but before taking out of bypass
 233         * assert/deassert outresetall
 234         */
 235        u32 mainvco = readl(&clock_manager_base->main_pll.vco);
 236
 237        /* assert main outresetall */
 238        writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
 239               &clock_manager_base->main_pll.vco);
 240
 241        u32 periphvco = readl(&clock_manager_base->per_pll.vco);
 242
 243        /* assert pheriph outresetall */
 244        writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
 245               &clock_manager_base->per_pll.vco);
 246
 247        /* assert sdram outresetall */
 248        writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
 249                CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
 250                &clock_manager_base->sdr_pll.vco);
 251
 252        /* deassert main outresetall */
 253        writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
 254               &clock_manager_base->main_pll.vco);
 255
 256        /* deassert pheriph outresetall */
 257        writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
 258               &clock_manager_base->per_pll.vco);
 259
 260        /* deassert sdram outresetall */
 261        writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
 262               &clock_manager_base->sdr_pll.vco);
 263
 264        /*
 265         * now that we've toggled outreset all, all the clocks
 266         * are aligned nicely; so we can change any phase.
 267         */
 268        ret = cm_write_with_phase(cfg->ddrdqsclk,
 269                                  &clock_manager_base->sdr_pll.ddrdqsclk,
 270                                  CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
 271        if (ret)
 272                return ret;
 273
 274        /* SDRAM DDR2XDQSCLK */
 275        ret = cm_write_with_phase(cfg->ddr2xdqsclk,
 276                                  &clock_manager_base->sdr_pll.ddr2xdqsclk,
 277                                  CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
 278        if (ret)
 279                return ret;
 280
 281        ret = cm_write_with_phase(cfg->ddrdqclk,
 282                                  &clock_manager_base->sdr_pll.ddrdqclk,
 283                                  CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
 284        if (ret)
 285                return ret;
 286
 287        ret = cm_write_with_phase(cfg->s2fuser2clk,
 288                                  &clock_manager_base->sdr_pll.s2fuser2clk,
 289                                  CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
 290        if (ret)
 291                return ret;
 292
 293        /* Take all three PLLs out of bypass when safe mode is cleared. */
 294        cm_write_bypass(0);
 295
 296        /* clear safe mode */
 297        cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
 298
 299        /*
 300         * now that safe mode is clear with clocks gated
 301         * it safe to change the source mux for the flashes the the L4_MAIN
 302         */
 303        writel(cfg->persrc, &clock_manager_base->per_pll.src);
 304        writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
 305
 306        /* Now ungate non-hw-managed clocks */
 307        writel(~0, &clock_manager_base->main_pll.en);
 308        writel(~0, &clock_manager_base->per_pll.en);
 309        writel(~0, &clock_manager_base->sdr_pll.en);
 310
 311        /* Clear the loss of lock bits (write 1 to clear) */
 312        writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
 313               CLKMGR_INTER_MAINPLLLOST_MASK,
 314               &clock_manager_base->inter);
 315
 316        return 0;
 317}
 318
 319static unsigned int cm_get_main_vco_clk_hz(void)
 320{
 321        u32 reg, clock;
 322
 323        /* get the main VCO clock */
 324        reg = readl(&clock_manager_base->main_pll.vco);
 325        clock = cm_get_osc_clk_hz(1);
 326        clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
 327                  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
 328        clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
 329                  CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
 330
 331        return clock;
 332}
 333
 334static unsigned int cm_get_per_vco_clk_hz(void)
 335{
 336        u32 reg, clock = 0;
 337
 338        /* identify PER PLL clock source */
 339        reg = readl(&clock_manager_base->per_pll.vco);
 340        reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
 341              CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
 342        if (reg == CLKMGR_VCO_SSRC_EOSC1)
 343                clock = cm_get_osc_clk_hz(1);
 344        else if (reg == CLKMGR_VCO_SSRC_EOSC2)
 345                clock = cm_get_osc_clk_hz(2);
 346        else if (reg == CLKMGR_VCO_SSRC_F2S)
 347                clock = cm_get_f2s_per_ref_clk_hz();
 348
 349        /* get the PER VCO clock */
 350        reg = readl(&clock_manager_base->per_pll.vco);
 351        clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
 352                  CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
 353        clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
 354                  CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
 355
 356        return clock;
 357}
 358
 359unsigned long cm_get_mpu_clk_hz(void)
 360{
 361        u32 reg, clock;
 362
 363        clock = cm_get_main_vco_clk_hz();
 364
 365        /* get the MPU clock */
 366        reg = readl(&clock_manager_base->altera.mpuclk);
 367        clock /= (reg + 1);
 368        reg = readl(&clock_manager_base->main_pll.mpuclk);
 369        clock /= (reg + 1);
 370        return clock;
 371}
 372
 373unsigned long cm_get_sdram_clk_hz(void)
 374{
 375        u32 reg, clock = 0;
 376
 377        /* identify SDRAM PLL clock source */
 378        reg = readl(&clock_manager_base->sdr_pll.vco);
 379        reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
 380              CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
 381        if (reg == CLKMGR_VCO_SSRC_EOSC1)
 382                clock = cm_get_osc_clk_hz(1);
 383        else if (reg == CLKMGR_VCO_SSRC_EOSC2)
 384                clock = cm_get_osc_clk_hz(2);
 385        else if (reg == CLKMGR_VCO_SSRC_F2S)
 386                clock = cm_get_f2s_sdr_ref_clk_hz();
 387
 388        /* get the SDRAM VCO clock */
 389        reg = readl(&clock_manager_base->sdr_pll.vco);
 390        clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
 391                  CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
 392        clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
 393                  CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
 394
 395        /* get the SDRAM (DDR_DQS) clock */
 396        reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
 397        reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
 398              CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
 399        clock /= (reg + 1);
 400
 401        return clock;
 402}
 403
 404unsigned int cm_get_l4_sp_clk_hz(void)
 405{
 406        u32 reg, clock = 0;
 407
 408        /* identify the source of L4 SP clock */
 409        reg = readl(&clock_manager_base->main_pll.l4src);
 410        reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
 411              CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
 412
 413        if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
 414                clock = cm_get_main_vco_clk_hz();
 415
 416                /* get the clock prior L4 SP divider (main clk) */
 417                reg = readl(&clock_manager_base->altera.mainclk);
 418                clock /= (reg + 1);
 419                reg = readl(&clock_manager_base->main_pll.mainclk);
 420                clock /= (reg + 1);
 421        } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
 422                clock = cm_get_per_vco_clk_hz();
 423
 424                /* get the clock prior L4 SP divider (periph_base_clk) */
 425                reg = readl(&clock_manager_base->per_pll.perbaseclk);
 426                clock /= (reg + 1);
 427        }
 428
 429        /* get the L4 SP clock which supplied to UART */
 430        reg = readl(&clock_manager_base->main_pll.maindiv);
 431        reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
 432              CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
 433        clock = clock / (1 << reg);
 434
 435        return clock;
 436}
 437
 438unsigned int cm_get_mmc_controller_clk_hz(void)
 439{
 440        u32 reg, clock = 0;
 441
 442        /* identify the source of MMC clock */
 443        reg = readl(&clock_manager_base->per_pll.src);
 444        reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
 445              CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
 446
 447        if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
 448                clock = cm_get_f2s_per_ref_clk_hz();
 449        } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
 450                clock = cm_get_main_vco_clk_hz();
 451
 452                /* get the SDMMC clock */
 453                reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
 454                clock /= (reg + 1);
 455        } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
 456                clock = cm_get_per_vco_clk_hz();
 457
 458                /* get the SDMMC clock */
 459                reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
 460                clock /= (reg + 1);
 461        }
 462
 463        /* further divide by 4 as we have fixed divider at wrapper */
 464        clock /= 4;
 465        return clock;
 466}
 467
 468unsigned int cm_get_qspi_controller_clk_hz(void)
 469{
 470        u32 reg, clock = 0;
 471
 472        /* identify the source of QSPI clock */
 473        reg = readl(&clock_manager_base->per_pll.src);
 474        reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
 475              CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
 476
 477        if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
 478                clock = cm_get_f2s_per_ref_clk_hz();
 479        } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
 480                clock = cm_get_main_vco_clk_hz();
 481
 482                /* get the qspi clock */
 483                reg = readl(&clock_manager_base->main_pll.mainqspiclk);
 484                clock /= (reg + 1);
 485        } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
 486                clock = cm_get_per_vco_clk_hz();
 487
 488                /* get the qspi clock */
 489                reg = readl(&clock_manager_base->per_pll.perqspiclk);
 490                clock /= (reg + 1);
 491        }
 492
 493        return clock;
 494}
 495
 496unsigned int cm_get_spi_controller_clk_hz(void)
 497{
 498        u32 reg, clock = 0;
 499
 500        clock = cm_get_per_vco_clk_hz();
 501
 502        /* get the clock prior L4 SP divider (periph_base_clk) */
 503        reg = readl(&clock_manager_base->per_pll.perbaseclk);
 504        clock /= (reg + 1);
 505
 506        return clock;
 507}
 508
 509/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
 510int dw_spi_get_clk(struct udevice *bus, ulong *rate)
 511{
 512        *rate = cm_get_spi_controller_clk_hz();
 513
 514        return 0;
 515}
 516
 517void cm_print_clock_quick_summary(void)
 518{
 519        printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
 520        printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
 521        printf("EOSC1       %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
 522        printf("EOSC2       %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
 523        printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
 524        printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
 525        printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
 526        printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
 527        printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
 528        printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
 529}
 530