LXR uboot/arch/arm/mach-socfpga/spl

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   4 */
   5
   6#include <common.h>
   7#include <asm/io.h>
   8#include <asm/u-boot.h>
   9#include <asm/utils.h>
  10#include <image.h>
  11#include <asm/arch/reset_manager.h>
  12#include <spl.h>
  13#include <asm/arch/system_manager.h>
  14#include <asm/arch/freeze_controller.h>
  15#include <asm/arch/clock_manager.h>
  16#include <asm/arch/misc.h>
  17#include <asm/arch/scan_manager.h>
  18#include <asm/arch/sdram.h>
  19#include <asm/sections.h>
  20#include <debug_uart.h>
  21#include <fdtdec.h>
  22#include <watchdog.h>
  23#include <dm/uclass.h>
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27static const struct socfpga_system_manager *sysmgr_regs =
  28        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  29
  30u32 spl_boot_device(void)
  31{
  32        const u32 bsel = readl(&sysmgr_regs->bootinfo);
  33
  34        switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  35        case 0x1:       /* FPGA (HPS2FPGA Bridge) */
  36                return BOOT_DEVICE_RAM;
  37        case 0x2:       /* NAND Flash (1.8V) */
  38        case 0x3:       /* NAND Flash (3.0V) */
  39                return BOOT_DEVICE_NAND;
  40        case 0x4:       /* SD/MMC External Transceiver (1.8V) */
  41        case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
  42                return BOOT_DEVICE_MMC1;
  43        case 0x6:       /* QSPI Flash (1.8V) */
  44        case 0x7:       /* QSPI Flash (3.0V) */
  45                return BOOT_DEVICE_SPI;
  46        default:
  47                printf("Invalid boot device (bsel=%08x)!\n", bsel);
  48                hang();
  49        }
  50}
  51
  52#ifdef CONFIG_SPL_MMC_SUPPORT
  53u32 spl_boot_mode(const u32 boot_device)
  54{
  55#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  56        return MMCSD_MODE_FS;
  57#else
  58        return MMCSD_MODE_RAW;
  59#endif
  60}
  61#endif
  62
  63void board_init_f(ulong dummy)
  64{
  65        const struct cm_config *cm_default_cfg = cm_get_default_config();
  66        unsigned long reg;
  67        int ret;
  68        struct udevice *dev;
  69
  70        /*
  71         * First C code to run. Clear fake OCRAM ECC first as SBE
  72         * and DBE might triggered during power on
  73         */
  74        reg = readl(&sysmgr_regs->eccgrp_ocram);
  75        if (reg & SYSMGR_ECC_OCRAM_SERR)
  76                writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
  77                       &sysmgr_regs->eccgrp_ocram);
  78        if (reg & SYSMGR_ECC_OCRAM_DERR)
  79                writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
  80                       &sysmgr_regs->eccgrp_ocram);
  81
  82        socfpga_sdram_remap_zero();
  83        socfpga_pl310_clear();
  84
  85        debug("Freezing all I/O banks\n");
  86        /* freeze all IO banks */
  87        sys_mgr_frzctrl_freeze_req();
  88
  89        /* Put everything into reset but L4WD0. */
  90        socfpga_per_reset_all();
  91
  92        if (!socfpga_is_booting_from_fpga()) {
  93                /* Put FPGA bridges into reset too. */
  94                socfpga_bridges_reset(1);
  95        }
  96
  97        socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
  98        timer_init();
  99
 100        debug("Reconfigure Clock Manager\n");
 101        /* reconfigure the PLLs */
 102        if (cm_basic_init(cm_default_cfg))
 103                hang();
 104
 105        /* Enable bootrom to configure IOs. */
 106        sysmgr_config_warmrstcfgio(1);
 107
 108        /* configure the IOCSR / IO buffer settings */
 109        if (scan_mgr_configure_iocsr())
 110                hang();
 111
 112        sysmgr_config_warmrstcfgio(0);
 113
 114        /* configure the pin muxing through system manager */
 115        sysmgr_config_warmrstcfgio(1);
 116        sysmgr_pinmux_init();
 117        sysmgr_config_warmrstcfgio(0);
 118
 119        /* Set bridges handoff value */
 120        socfpga_bridges_set_handoff_regs(true, true, true);
 121
 122        debug("Unfreezing/Thaw all I/O banks\n");
 123        /* unfreeze / thaw all IO banks */
 124        sys_mgr_frzctrl_thaw_req();
 125
 126#ifdef CONFIG_DEBUG_UART
 127        socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 128        debug_uart_init();
 129#endif
 130
 131        ret = spl_early_init();
 132        if (ret) {
 133                debug("spl_early_init() failed: %d\n", ret);
 134                hang();
 135        }
 136
 137        ret = uclass_get_device(UCLASS_RESET, 0, &dev);
 138        if (ret)
 139                debug("Reset init failed: %d\n", ret);
 140
 141#ifdef CONFIG_SPL_NAND_DENALI
 142        struct socfpga_reset_manager *reset_manager_base =
 143                (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
 144
 145        clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4));
 146#endif
 147
 148        /* enable console uart printing */
 149        preloader_console_init();
 150
 151        ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 152        if (ret) {
 153                debug("DRAM init failed: %d\n", ret);
 154                hang();
 155        }
 156}
 157