LXR uboot/arch/powerpc/cpu/mpc85xx/bsc9132

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2013 Freescale Semiconductor, Inc.
   4 * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
   5 */
   6
   7#include <config.h>
   8#include <common.h>
   9#include <asm/io.h>
  10#include <asm/immap_85xx.h>
  11#include <asm/fsl_serdes.h>
  12
  13#define SRDS1_MAX_LANES         4
  14
  15static u32 serdes1_prtcl_map;
  16
  17static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  18         [0] = {NONE, NONE, NONE, NONE},
  19         [1] = {PCIE1, PCIE2, CPRI2, CPRI1},
  20         [2] = {PCIE1, PCIE2, CPRI2, CPRI1},
  21         [3] = {PCIE1, PCIE2, CPRI2, CPRI1},
  22         [4] = {PCIE1, PCIE2, CPRI2, CPRI1},
  23         [5] = {PCIE1, PCIE2, CPRI2, CPRI1},
  24         [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  25         [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  26         [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  27         [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  28        [10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  29        [11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
  30        [12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  31        [13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  32        [14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  33        [15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  34        [16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  35        [17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  36        [18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  37        [19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  38        [20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  39        [21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  40        [22] = {PCIE1, PCIE2, CPRI2, CPRI1},
  41        [23] = {PCIE1, PCIE2, CPRI2, CPRI1},
  42        [24] = {PCIE1, PCIE2, CPRI2, CPRI1},
  43        [25] = {PCIE1, PCIE2, CPRI2, CPRI1},
  44        [26] = {PCIE1, PCIE2, CPRI2, CPRI1},
  45        [27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  46        [28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  47        [29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  48        [30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  49        [31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  50        [32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
  51        [33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  52        [34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  53        [35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  54        [36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  55        [37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  56        [38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  57        [39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  58        [40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  59        [41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  60        [42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  61        [43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  62        [44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  63        [45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  64        [46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  65        [47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  66};
  67
  68int is_serdes_configured(enum srds_prtcl prtcl)
  69{
  70        if (!(serdes1_prtcl_map & (1 << NONE)))
  71                fsl_serdes_init();
  72
  73        return (1 << prtcl) & serdes1_prtcl_map;
  74}
  75
  76void fsl_serdes_init(void)
  77{
  78        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  79        u32 pordevsr = in_be32(&gur->pordevsr);
  80        u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  81                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  82        int lane;
  83
  84        if (serdes1_prtcl_map & (1 << NONE))
  85                return;
  86
  87        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
  88
  89        if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  90                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  91                return;
  92        }
  93
  94        for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  95                enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
  96                serdes1_prtcl_map |= (1 << lane_prtcl);
  97        }
  98
  99        /* Set the first bit to indicate serdes has been initialized */
 100        serdes1_prtcl_map |= (1 << NONE);
 101}
 102