LXR uboot/arch/powerpc/cpu/mpc86xx/interrupts.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2000-2002
   4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 *
   6 * (C) Copyright 2002 (440 port)
   7 * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
   8 *
   9 * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
  10 * Xianghua Xiao (X.Xiao@motorola.com)
  11 *
  12 * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
  13 * Jeff Brown
  14 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  15 */
  16
  17#include <common.h>
  18#include <irq_func.h>
  19#include <mpc86xx.h>
  20#include <command.h>
  21#include <asm/processor.h>
  22#ifdef CONFIG_POST
  23#include <post.h>
  24#endif
  25
  26void interrupt_init_cpu(unsigned *decrementer_count)
  27{
  28        volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  29        volatile ccsr_pic_t *pic = &immr->im_pic;
  30
  31#ifdef CONFIG_POST
  32        /*
  33         * The POST word is stored in the PIC's TFRR register which gets
  34         * cleared when the PIC is reset.  Save it off so we can restore it
  35         * later.
  36         */
  37        ulong post_word = post_word_load();
  38#endif
  39
  40        pic->gcr = MPC86xx_PICGCR_RST;
  41        while (pic->gcr & MPC86xx_PICGCR_RST)
  42                ;
  43        pic->gcr = MPC86xx_PICGCR_MODE;
  44
  45        *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
  46        debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %d\n",
  47              (get_tbclk() / 1000000),
  48              *decrementer_count);
  49
  50#ifdef CONFIG_INTERRUPTS
  51
  52        pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
  53        debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
  54
  55        pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
  56        debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
  57
  58        pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
  59        debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
  60
  61#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
  62        pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
  63        debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
  64#endif
  65#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
  66        pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
  67        debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
  68#endif
  69
  70        pic->ctpr = 0;  /* 40080 clear current task priority register */
  71#endif
  72
  73#ifdef CONFIG_POST
  74        post_word_store(post_word);
  75#endif
  76}
  77
  78/*
  79 * timer_interrupt - gets called when the decrementer overflows,
  80 * with interrupts disabled.
  81 * Trivial implementation - no need to be really accurate.
  82 */
  83void timer_interrupt_cpu(struct pt_regs *regs)
  84{
  85        /* nothing to do here */
  86}
  87
  88/*
  89 * Install and free a interrupt handler. Not implemented yet.
  90 */
  91void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
  92{
  93}
  94
  95void irq_free_handler(int vec)
  96{
  97}
  98
  99/*
 100 * irqinfo - print information about PCI devices,not implemented.
 101 */
 102int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 103{
 104        return 0;
 105}
 106
 107/*
 108 * Handle external interrupts
 109 */
 110void external_interrupt(struct pt_regs *regs)
 111{
 112        puts("external_interrupt(oops!)\n");
 113}
 114