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12#include <asm/arch/clock.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/iomux.h>
15#include <asm/arch/mx6-pins.h>
16#include <linux/errno.h>
17#include <asm/gpio.h>
18#include <asm/mach-imx/iomux-v3.h>
19#include <asm/mach-imx/boot_mode.h>
20#include <asm/mach-imx/mxc_i2c.h>
21#include <asm/mach-imx/video.h>
22#include <mmc.h>
23#include <fsl_esdhc_imx.h>
24#include <miiphy.h>
25#include <netdev.h>
26#include <asm/arch/mxc_hdmi.h>
27#include <asm/arch/crm_regs.h>
28#include <linux/fb.h>
29#include <ipu_pixfmt.h>
30#include <asm/io.h>
31#include <asm/arch/sys_proto.h>
32#include <pwm.h>
33
34struct i2c_pads_info i2c_pad_info3 = {
35 .scl = {
36 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
37 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
38 .gp = IMX_GPIO_NR(3, 17)
39 },
40 .sda = {
41 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
42 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
43 .gp = IMX_GPIO_NR(3, 18)
44 }
45};
46
47iomux_v3_cfg_t const uart1_pads[] = {
48 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
49 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
50};
51
52iomux_v3_cfg_t const uart5_pads[] = {
53 MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
54 MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
55};
56
57iomux_v3_cfg_t const gpio_pads[] = {
58
59 MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
60
61 MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
62
63 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
64
65 MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
66
67 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
68
69 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
70
71 MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
72
73 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
74
75 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
76
77 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
78};
79
80static iomux_v3_cfg_t const misc_pads[] = {
81 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
82
83 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
84 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
85};
86
87iomux_v3_cfg_t const enet_pads[] = {
88 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
89 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
98};
99
100static void setup_iomux_enet(void)
101{
102 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
103
104 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
105
106
107 setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
108}
109
110static iomux_v3_cfg_t const backlight_pads[] = {
111 MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
112 MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
113 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
114};
115
116iomux_v3_cfg_t const ecspi4_pads[] = {
117 MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
118 MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
119 MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
120 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
121};
122
123static iomux_v3_cfg_t const display_pads[] = {
124 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
125 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
126 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
127 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
128 MX6_PAD_DI0_PIN4__GPIO4_IO20,
129 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
130 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
131 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
132 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
133 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
134 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
135 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
136 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
137 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
138 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
139 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
140 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
141 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
142 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
143 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
144 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
145 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
146 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
147 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
148 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
149 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
150 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
151 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
152 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
153};
154
155int board_spi_cs_gpio(unsigned bus, unsigned cs)
156{
157 return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
158 ? (IMX_GPIO_NR(3, 20)) : -1;
159}
160
161static void setup_spi(void)
162{
163 int i;
164
165 imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
166 for (i = 0; i < 3; i++)
167 enable_spi_clk(true, i);
168
169
170 gpio_direction_output(ECSPI4_CS1, 1);
171}
172
173static void setup_iomux_uart(void)
174{
175 imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
176}
177
178int board_eth_init(bd_t *bis)
179{
180 struct iomuxc *iomuxc_regs =
181 (struct iomuxc *)IOMUXC_BASE_ADDR;
182 int ret;
183
184
185 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
186
187 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
188 if (ret)
189 return ret;
190
191 setup_iomux_enet();
192 return cpu_eth_init(bis);
193}
194
195static void enable_lvds(struct display_info_t const *dev)
196{
197 imx_iomux_v3_setup_multiple_pads(
198 display_pads,
199 ARRAY_SIZE(display_pads));
200 imx_iomux_v3_setup_multiple_pads(
201 backlight_pads,
202 ARRAY_SIZE(backlight_pads));
203
204
205 if (pwm_init(2, 0, 0))
206 goto error;
207
208 if (pwm_config(2, 500, 3000))
209 goto error;
210 if (pwm_enable(2))
211 goto error;
212 return;
213
214error:
215 puts("error init pwm for backlight\n");
216 return;
217}
218
219static void setup_display(void)
220{
221 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
222 int reg;
223
224 enable_ipu_clock();
225
226 reg = readl(&mxc_ccm->cs2cdr);
227
228 reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
229 reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
230 writel(reg, &mxc_ccm->cs2cdr);
231
232 imx_iomux_v3_setup_multiple_pads(backlight_pads,
233 ARRAY_SIZE(backlight_pads));
234}
235
236static void setup_iomux_gpio(void)
237{
238 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
239}
240
241int board_early_init_f(void)
242{
243 setup_iomux_uart();
244 setup_iomux_gpio();
245
246 setup_display();
247 return 0;
248}
249
250
251static void setup_i2c4(void)
252{
253
254 gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
255 gpio_direction_input(IMX_GPIO_NR(1, 7));
256 gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
257 gpio_direction_input(IMX_GPIO_NR(1, 8));
258}
259
260static void setup_board_gpio(void)
261{
262
263 gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
264 gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
265
266 gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
267 gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
268 gpio_request(IMX_GPIO_NR(1, 4), "LED red");
269 gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
270 gpio_request(IMX_GPIO_NR(1, 5), "LED green");
271 gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
272 gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
273 gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
274}
275
276static void setup_board_spi(void)
277{
278}
279
