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6#include <init.h>
7#include <asm/arch/clock.h>
8#include <asm/arch/iomux.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/crm_regs.h>
11#include <asm/arch/mx6ul_pins.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/gpio.h>
15#include <asm/mach-imx/iomux-v3.h>
16#include <asm/mach-imx/boot_mode.h>
17#include <asm/mach-imx/mxc_i2c.h>
18#include <asm/io.h>
19#include <common.h>
20#include <env.h>
21#include <fsl_esdhc_imx.h>
22#include <i2c.h>
23#include <miiphy.h>
24#include <mmc.h>
25#include <netdev.h>
26#include <usb.h>
27#include <usb/ehci-ci.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
33 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
34
35#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
36 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38
39#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
41 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
42 PAD_CTL_ODE)
43
44#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
45 PAD_CTL_SPEED_HIGH | \
46 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
47
48#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
49 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
50
51#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
52
53#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
54 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
55
56#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
57 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
58 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
59 PAD_CTL_SRE_FAST)
60
61#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
62
63static struct i2c_pads_info i2c_pad_info1 = {
64 .scl = {
65 .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
66 .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
67 .gp = IMX_GPIO_NR(1, 2),
68 },
69 .sda = {
70 .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
71 .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
72 .gp = IMX_GPIO_NR(1, 3),
73 },
74};
75
76static struct i2c_pads_info i2c_pad_info2 = {
77 .scl = {
78 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C2_SCL | PC,
79 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC,
80 .gp = IMX_GPIO_NR(1, 0),
81 },
82 .sda = {
83 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC,
84 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC,
85 .gp = IMX_GPIO_NR(1, 1),
86 },
87};
88
89static struct i2c_pads_info i2c_pad_info4 = {
90 .scl = {
91 .i2c_mode = MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC,
92 .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC,
93 .gp = IMX_GPIO_NR(1, 20),
94 },
95 .sda = {
96 .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC,
97 .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC,
98 .gp = IMX_GPIO_NR(1, 21),
99 },
100};
101
102int dram_init(void)
103{
104 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
105
106 return 0;
107}
108
109static iomux_v3_cfg_t const uart1_pads[] = {
110 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
111 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
112 MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
113 MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
114};
115
116static iomux_v3_cfg_t const uart4_pads[] = {
117 MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
118 MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
119};
120
121static iomux_v3_cfg_t const uart5_pads[] = {
122 MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
123 MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
124 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
125 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
126};
127
128static iomux_v3_cfg_t const uart7_pads[] = {
129 MX6_PAD_ENET2_RX_EN__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
130 MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
131};
132
133static iomux_v3_cfg_t const uart8_pads[] = {
134 MX6_PAD_LCD_DATA20__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
135 MX6_PAD_LCD_DATA21__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
136};
137
138static void setup_iomux_uart(void)
139{
140 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
141 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
142 imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
143 imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));
144 imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads));
145}
146
147
148static iomux_v3_cfg_t const usdhc2_pads[] = {
149 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
157 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159
160
161
162
163 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
164};
165
166static struct fsl_esdhc_cfg usdhc_cfg = {
167 .esdhc_base = USDHC2_BASE_ADDR,
168 .max_bus_width = 8,
169};
170
171#define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9)
172
173int board_mmc_getcd(struct mmc *mmc)
174{
175
176 return 1;
177}
178
179int board_mmc_init(bd_t *bis)
180{
181 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
182
183 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
184
185 return fsl_esdhc_initialize(bis, &usdhc_cfg);
186}
187
188#define USB_OTHERREGS_OFFSET 0x800
189#define UCTRL_PWR_POL (1 << 9)
190
191static iomux_v3_cfg_t const usb_otg_pads[] = {
192
193 MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
194 MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
195
196 MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
197 MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
198};
199
200static void setup_usb(void)
201{
202 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
203 ARRAY_SIZE(usb_otg_pads));
204}
205
206int board_usb_phy_mode(int port)
207{
208 if (port == 1)
209 return USB_INIT_HOST;
210 else
211 return usb_phy_mode(port);
212}
213
214int board_ehci_hcd_init(int port)
215{
216 u32 *usbnc_usb_ctrl;
217
218 if (port > 1)
219 return -EINVAL;
220
221 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
222 port * 4);
223
224
225 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
226
227 return 0;
228}
229
230static iomux_v3_cfg_t const fec1_pads[] = {
231 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
232 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
233 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
234 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
235 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
236 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
237 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
238 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
239 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
240 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
241
242
243 MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
244
245 MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
246};
247
248#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17)
249
250int board_eth_init(bd_t *bis)
251{
252 int ret;
253
254 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
255
256
257 ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
258 if (!ret)
259 gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
260 mdelay(10);
261 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
262 mdelay(10);
263
264 return cpu_eth_init(bis);
265}
266
267static int setup_fec(int fec_id)
268{
269 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
270 int ret;
271
272
273
274
275
276 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
277 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
278
279 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
280 if (ret)
281 return ret;
282
283 enable_enet_clk(1);
284
285 return 0;
286}
287
288int board_phy_config(struct phy_device *phydev)
289{
290 if (phydev->drv->config)
291 phydev->drv->config(phydev);
292
293 return 0;
294}
295
296int board_early_init_f(void)
297{
298 setup_iomux_uart();
299
300 return 0;
301}
302
303int board_init(void)
304{
305
306 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
307
308 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
309 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
310 setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
311
312 setup_fec(CONFIG_FEC_ENET_DEV);
313
314 setup_usb();
315
316 return 0;
317}
318
319static const struct boot_mode board_boot_modes[] = {
320
321 {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)},
322 { NULL, 0 },
323};
324
325int board_late_init(void)
326{
327 add_board_boot_modes(board_boot_modes);
328 env_set("board_name", "xpress");
329
330 return 0;
331}
332
333int checkboard(void)
334{
335 puts("Board: CCV-EVA xPress\n");
336
337 return 0;
338}
339
