LXR uboot/board/compulab/cl-som-imx7/mux.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * SPL/U-Boot mux functions for CompuLab CL-SOM-iMX7 module
   4 *
   5 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
   6 *
   7 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
   8 */
   9
  10#include <common.h>
  11#include <asm/mach-imx/iomux-v3.h>
  12#include <asm/arch-mx7/mx7-pins.h>
  13
  14#define PADS_SET(pads_array)                                                   \
  15void cl_som_imx7_##pads_array##_set(void)                                      \
  16{                                                                              \
  17        imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array));  \
  18}
  19
  20#ifdef CONFIG_FSL_ESDHC_IMX
  21
  22#define USDHC_PAD_CTRL          (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  23                                PAD_CTL_HYS | PAD_CTL_PUE | \
  24                                PAD_CTL_PUS_PU47KOHM)
  25
  26static iomux_v3_cfg_t const usdhc1_pads[] = {
  27        MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  28        MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  29        MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  30        MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  31        MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  32        MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  33
  34        MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  35};
  36
  37PADS_SET(usdhc1_pads)
  38
  39#endif /* CONFIG_FSL_ESDHC_IMX */
  40
  41#define UART_PAD_CTRL           (PAD_CTL_DSE_3P3V_49OHM | \
  42                                PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  43
  44static iomux_v3_cfg_t const uart1_pads[] = {
  45        MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  46        MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  47};
  48
  49PADS_SET(uart1_pads)
  50
  51#ifdef CONFIG_SPI
  52
  53#define SPI_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \
  54                        PAD_CTL_DSE_3P3V_32OHM)
  55
  56#define GPIO_PAD_CTRL   (PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \
  57                        PAD_CTL_SRE_SLOW)
  58
  59static iomux_v3_cfg_t const espi1_pads[] = {
  60        MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  61        MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  62        MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  63        MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  64};
  65
  66PADS_SET(espi1_pads)
  67
  68#endif /* CONFIG_SPI */
  69
  70#ifndef CONFIG_SPL_BUILD
  71
  72#ifdef CONFIG_FSL_ESDHC_IMX
  73
  74static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
  75        MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76        MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77        MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78        MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79        MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80        MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81        MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82        MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83        MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84        MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85        MX7D_PAD_SD3_STROBE__SD3_STROBE  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86
  87        MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88};
  89
  90PADS_SET(usdhc3_emmc_pads)
  91
  92#endif /* CONFIG_FSL_ESDHC_IMX */
  93
  94#ifdef CONFIG_FEC_MXC
  95
  96#define ENET_PAD_CTRL           (PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  97#define ENET_PAD_CTRL_MII       (PAD_CTL_PUS_PU5KOHM)
  98
  99static iomux_v3_cfg_t const phy1_rst_pads[] = {
 100        /* PHY1 RST */
 101        MX7D_PAD_GPIO1_IO04__GPIO1_IO4  | MUX_PAD_CTRL(GPIO_PAD_CTRL),
 102};
 103
 104PADS_SET(phy1_rst_pads)
 105
 106static iomux_v3_cfg_t const fec1_pads[] = {
 107        MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL |
 108        MUX_PAD_CTRL(ENET_PAD_CTRL),
 109        MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 110        MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 111        MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112        MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 113        MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 114        MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL |
 115        MUX_PAD_CTRL(ENET_PAD_CTRL),
 116        MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117        MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118        MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119        MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120        MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 121        MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 122        MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 123};
 124
 125PADS_SET(fec1_pads)
 126
 127#endif /* CONFIG_FEC_MXC */
 128
 129static iomux_v3_cfg_t const usb_otg1_pads[] = {
 130        MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 131};
 132
 133PADS_SET(usb_otg1_pads)
 134
 135static iomux_v3_cfg_t const wdog_pads[] = {
 136        MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 137};
 138
 139PADS_SET(wdog_pads)
 140
 141#endif /* !CONFIG_SPL_BUILD */
 142