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10#include <common.h>
11#include <env.h>
12#include <hwconfig.h>
13#include <init.h>
14#include <mpc8xx.h>
15#include <fdt_support.h>
16#include <serial.h>
17#include <asm/io.h>
18#include <dm/uclass.h>
19#include <wdt.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23#define SDRAM_MAX_SIZE (32 * 1024 * 1024)
24
25static const uint cs1_dram_table_66[] = {
26
27 0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
28 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
29
30
31 0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
32 0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
33 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
34 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
35
36
37 0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
38 0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
39
40
41 0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
42 0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
43 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
44 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
45
46
47 0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
48 0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
49
50
51 0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
52
53
54 0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
55};
56
57int ft_board_setup(void *blob, bd_t *bd)
58{
59 const char *sync = "receive";
60
61 ft_cpu_setup(blob, bd);
62
63
64 do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
65 bd->bi_busfreq, 1);
66
67
68 fdt_fixup_ethernet(blob);
69
70
71 do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
72
73
74 do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
75
76
77 do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
78
79
80 do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
81 sync, strlen(sync), 1);
82
83 return 0;
84}
85
86int checkboard(void)
87{
88 serial_puts("BOARD: MCR3000 CSSI\n");
89
90 return 0;
91}
92
93int dram_init(void)
94{
95 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
96 memctl8xx_t __iomem *memctl = &immap->im_memctl;
97
98 printf("UPMA init for SDRAM (CAS latency 2), ");
99 printf("init address 0x%08x, size ", (int)dram_init);
100
101 upmconfig(UPMA, (uint *)cs1_dram_table_66,
102 sizeof(cs1_dram_table_66) / sizeof(uint));
103 udelay(10);
104 out_be16(&memctl->memc_mptpr, 0x0200);
105 out_be32(&memctl->memc_mamr, 0x14904000);
106 udelay(10);
107 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
108 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
109 udelay(10);
110 out_be32(&memctl->memc_mcr, 0x80002830);
111 out_be32(&memctl->memc_mar, 0x00000088);
112 out_be32(&memctl->memc_mcr, 0x80002038);
113 udelay(200);
114
115 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
116 SDRAM_MAX_SIZE);
117
118 return 0;
119}
120
121int misc_init_r(void)
122{
123 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
124 iop8xx_t __iomem *iop = &immr->im_ioport;
125
126
127 clrbits_be16(&iop->iop_pcpar, 0x4);
128 clrbits_be16(&iop->iop_pcdir, 0x4);
129
130
131 if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
132 env_set("bootdelay", "60");
133
134 return 0;
135}
136
137int board_early_init_f(void)
138{
139 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
140
141
142
143
144 clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000);
145 setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000);
146 udelay(1);
147 setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000);
148
149 return 0;
150}
151
152int board_early_init_r(void)
153{
154 struct udevice *watchdog_dev = NULL;
155
156 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
157 puts("Cannot find watchdog!\n");
158 } else {
159 puts("Enabling watchdog.\n");
160 wdt_start(watchdog_dev, 0xffff, 0);
161 }
162
163 return 0;
164}
165