LXR uboot/board/esd/meesc/meesc.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2007-2008
   4 * Stelian Pop <stelian@popies.net>
   5 * Lead Tech Design <www.leadtechdesign.com>
   6 *
   7 * (C) Copyright 2009-2015
   8 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
   9 * esd electronic system design gmbh <www.esd.eu>
  10 */
  11
  12#include <common.h>
  13#include <env.h>
  14#include <serial.h>
  15#include <vsprintf.h>
  16#include <asm/io.h>
  17#include <asm/gpio.h>
  18#include <asm/mach-types.h>
  19#include <asm/setup.h>
  20#include <asm/arch/at91sam9_smc.h>
  21#include <asm/arch/at91_common.h>
  22#include <asm/arch/at91_pmc.h>
  23#include <asm/arch/at91_rstc.h>
  24#include <asm/arch/at91_matrix.h>
  25#include <asm/arch/at91_pio.h>
  26#include <asm/arch/clk.h>
  27#include <netdev.h>
  28
  29DECLARE_GLOBAL_DATA_PTR;
  30
  31/*
  32 * Miscelaneous platform dependent initialisations
  33 */
  34
  35#ifdef CONFIG_REVISION_TAG
  36static int hw_rev = -1; /* hardware revision */
  37
  38int get_hw_rev(void)
  39{
  40        if (hw_rev >= 0)
  41                return hw_rev;
  42
  43        hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
  44        hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
  45        hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
  46        hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
  47
  48        if (hw_rev == 15)
  49                hw_rev = 0;
  50
  51        return hw_rev;
  52}
  53#endif /* CONFIG_REVISION_TAG */
  54
  55#ifdef CONFIG_CMD_NAND
  56static void meesc_nand_hw_init(void)
  57{
  58        unsigned long csa;
  59        at91_smc_t      *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  60        at91_matrix_t   *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  61
  62        /* Enable CS3 */
  63        csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  64        writel(csa, &matrix->csa[0]);
  65
  66        /* Configure SMC CS3 for NAND/SmartMedia */
  67        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  68                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
  69                &smc->cs[3].setup);
  70
  71        writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  72                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  73                &smc->cs[3].pulse);
  74
  75        writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
  76                &smc->cs[3].cycle);
  77        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  78                AT91_SMC_MODE_EXNW_DISABLE |
  79                AT91_SMC_MODE_DBW_8 |
  80                AT91_SMC_MODE_TDF_CYCLE(12),
  81                &smc->cs[3].mode);
  82
  83        /* Configure RDY/BSY */
  84        gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  85
  86        /* Enable NandFlash */
  87        gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  88}
  89#endif /* CONFIG_CMD_NAND */
  90
  91#ifdef CONFIG_MACB
  92static void meesc_macb_hw_init(void)
  93{
  94        at91_periph_clk_enable(ATMEL_ID_EMAC);
  95
  96        at91_macb_hw_init();
  97}
  98#endif
  99
 100/*
 101 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
 102 * controller debugging
 103 * The ET1100 is located at physical address 0x70000000
 104 * Its process memory is located at physical address 0x70001000
 105 */
 106static void meesc_ethercat_hw_init(void)
 107{
 108        at91_smc_t      *smc1   = (at91_smc_t *) ATMEL_BASE_SMC1;
 109
 110        /* Configure SMC EBI1_CS0 for EtherCAT */
 111        writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
 112                AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
 113                &smc1->cs[0].setup);
 114        writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
 115                AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
 116                &smc1->cs[0].pulse);
 117        writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
 118                &smc1->cs[0].cycle);
 119        /*
 120         * Configure behavior at external wait signal, byte-select mode, 16 bit
 121         * data bus width, none data float wait states and TDF optimization
 122         */
 123        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
 124                AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
 125                AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
 126
 127        /* Configure RDY/BSY */
 128        at91_set_b_periph(AT91_PIO_PORTE, 20, 0);       /* EBI1_NWAIT */
 129}
 130
 131int dram_init(void)
 132{
 133        /* dram_init must store complete ramsize in gd->ram_size */
 134        gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 135                                PHYS_SDRAM_SIZE);
 136        return 0;
 137}
 138
 139int dram_init_banksize(void)
 140{
 141        gd->bd->bi_dram[0].start = PHYS_SDRAM;
 142        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 143
 144        return 0;
 145}
 146
 147int board_eth_init(bd_t *bis)
 148{
 149        int rc = 0;
 150#ifdef CONFIG_MACB
 151        rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 152#endif
 153        return rc;
 154}
 155
 156#ifdef CONFIG_DISPLAY_BOARDINFO
 157int checkboard(void)
 158{
 159        char str[32];
 160        u_char hw_type; /* hardware type */
 161
 162        /* read the "Type" register of the ET1100 controller */
 163        hw_type = readb(CONFIG_ET1100_BASE);
 164
 165        switch (hw_type) {
 166        case 0x11:
 167        case 0x3F:
 168                /* ET1100 present, arch number of MEESC-Board */
 169                gd->bd->bi_arch_number = MACH_TYPE_MEESC;
 170                puts("Board: CAN-EtherCAT Gateway");
 171                break;
 172        case 0xFF:
 173                /* no ET1100 present, arch number of EtherCAN/2-Board */
 174                gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
 175                puts("Board: EtherCAN/2 Gateway");
 176                /* switch on LED1D */
 177                at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
 178                break;
 179        default:
 180                /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
 181                gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
 182                printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
 183                puts("Board: EtherCAN/2 Gateway");
 184                break;
 185        }
 186        if (env_get_f("serial#", str, sizeof(str)) > 0) {
 187                puts(", serial# ");
 188                puts(str);
 189        }
 190#ifdef CONFIG_REVISION_TAG
 191        printf("\nHardware-revision: 1.%d\n", get_hw_rev());
 192#endif
 193        printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
 194        return 0;
 195}
 196#endif /* CONFIG_DISPLAY_BOARDINFO */
 197
 198#ifdef CONFIG_SERIAL_TAG
 199void get_board_serial(struct tag_serialnr *serialnr)
 200{
 201        char *str;
 202
 203        char *serial = env_get("serial#");
 204        if (serial) {
 205                str = strchr(serial, '_');
 206                if (str && (strlen(str) >= 4)) {
 207                        serialnr->high = (*(str + 1) << 8) | *(str + 2);
 208                        serialnr->low = simple_strtoul(str + 3, NULL, 16);
 209                }
 210        } else {
 211                serialnr->high = 0;
 212                serialnr->low = 0;
 213        }
 214}
 215#endif
 216
 217#ifdef CONFIG_REVISION_TAG
 218u32 get_board_rev(void)
 219{
 220        return hw_rev | 0x100;
 221}
 222#endif
 223
 224#ifdef CONFIG_MISC_INIT_R
 225int misc_init_r(void)
 226{
 227        char            *str;
 228        char            buf[32];
 229        at91_pmc_t      *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 230
 231        /*
 232         * Normally the processor clock has a divisor of 2.
 233         * In some cases this this needs to be set to 4.
 234         * Check the user has set environment mdiv to 4 to change the divisor.
 235         */
 236        str = env_get("mdiv");
 237        if (str && (strcmp(str, "4") == 0)) {
 238                writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
 239                        AT91SAM9_PMC_MDIV_4, &pmc->mckr);
 240                at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
 241                serial_setbrg();
 242                /* Notify the user that the clock is not default */
 243                printf("Setting master clock to %s MHz\n",
 244                        strmhz(buf, get_mck_clk_rate()));
 245        }
 246
 247        return 0;
 248}
 249#endif /* CONFIG_MISC_INIT_R */
 250
 251int board_early_init_f(void)
 252{
 253        at91_periph_clk_enable(ATMEL_ID_UHP);
 254
 255        return 0;
 256}
 257
 258int board_init(void)
 259{
 260        /* initialize ET1100 Controller */
 261        meesc_ethercat_hw_init();
 262
 263        /* adress of boot parameters */
 264        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 265
 266#ifdef CONFIG_CMD_NAND
 267        meesc_nand_hw_init();
 268#endif
 269#ifdef CONFIG_MACB
 270        meesc_macb_hw_init();
 271#endif
 272#ifdef CONFIG_AT91_CAN
 273        at91_can_hw_init();
 274#endif
 275#ifdef CONFIG_USB_OHCI_NEW
 276        at91_uhp_hw_init();
 277#endif
 278        return 0;
 279}
 280