LXR uboot/board/freescale/mpc8555cds/mpc8555cds.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2004, 2011 Freescale Semiconductor.
   4 */
   5
   6#include <common.h>
   7#include <init.h>
   8#include <pci.h>
   9#include <vsprintf.h>
  10#include <asm/processor.h>
  11#include <asm/mmu.h>
  12#include <asm/immap_85xx.h>
  13#include <fsl_ddr_sdram.h>
  14#include <ioports.h>
  15#include <spd_sdram.h>
  16#include <linux/libfdt.h>
  17#include <fdt_support.h>
  18
  19#include "../common/cadmus.h"
  20#include "../common/eeprom.h"
  21#include "../common/via.h"
  22
  23#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  24extern void ddr_enable_ecc(unsigned int dram_size);
  25#endif
  26
  27void local_bus_init(void);
  28
  29/*
  30 * I/O Port configuration table
  31 *
  32 * if conf is 1, then that port pin will be configured at boot time
  33 * according to the five values podr/pdir/ppar/psor/pdat for that entry
  34 */
  35
  36const iop_conf_t iop_conf_tab[4][32] = {
  37
  38    /* Port A configuration */
  39    {   /*            conf ppar psor pdir podr pdat */
  40        /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
  41        /* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
  42        /* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
  43        /* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
  44        /* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
  45        /* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
  46        /* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
  47        /* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
  48        /* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
  49        /* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
  50        /* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
  51        /* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
  52        /* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
  53        /* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
  54        /* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
  55        /* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
  56        /* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
  57        /* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
  58        /* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
  59        /* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
  60        /* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
  61        /* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
  62        /* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
  63        /* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
  64        /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  65        /* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
  66        /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  67        /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  68        /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  69        /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  70        /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
  71        /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  72    },
  73
  74    /* Port B configuration */
  75    {   /*            conf ppar psor pdir podr pdat */
  76        /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  77        /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  78        /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  79        /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  80        /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  81        /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  82        /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
  83        /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
  84        /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
  85        /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
  86        /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
  87        /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
  88        /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
  89        /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
  90        /* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
  91        /* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
  92        /* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
  93        /* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
  94        /* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
  95        /* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
  96        /* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
  97        /* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
  98        /* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
  99        /* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 100        /* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 101        /* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 102        /* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 103        /* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 104        /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 105        /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 106        /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 107        /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 108    },
 109
 110    /* Port C */
 111    {   /*            conf ppar psor pdir podr pdat */
 112        /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 113        /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 114        /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
 115        /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 116        /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
 117        /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 118        /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 119        /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 120        /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
 121        /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
 122        /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 123        /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 124        /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
 125        /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
 126        /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 127        /* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
 128        /* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
 129        /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 130        /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 131        /* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 132        /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
 133        /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
 134        /* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
 135        /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 136        /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 137        /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 138        /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 139        /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 140        /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 141        /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 142        /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 143        /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 144    },
 145
 146    /* Port D */
 147    {   /*            conf ppar psor pdir podr pdat */
 148        /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 149        /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 150        /* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
 151        /* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
 152        /* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
 153        /* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
 154        /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 155        /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 156        /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 157        /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 158        /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 159        /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 160        /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 161        /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 162        /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 163        /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
 164        /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 165        /* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
 166        /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 167        /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 168        /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 169        /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 170        /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 171        /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 172        /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 173        /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 174        /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 175        /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 176        /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 177        /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 178        /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 179        /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 180    }
 181};
 182
 183int checkboard (void)
 184{
 185        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 186        char buf[32];
 187
 188        /* PCI slot in USER bits CSR[6:7] by convention. */
 189        uint pci_slot = get_pci_slot ();
 190
 191        uint pci_dual = get_pci_dual ();        /* PCI DUAL in CM_PCI[3] */
 192        uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
 193        uint pci1_clk_sel = gur->porpllsr & 0x8000;     /* PORPLLSR[16] */
 194        uint pci2_clk_sel = gur->porpllsr & 0x4000;     /* PORPLLSR[17] */
 195
 196        uint pci1_speed = get_clock_freq ();    /* PCI PSPEED in [4:5] */
 197
 198        uint cpu_board_rev = get_cpu_board_revision ();
 199
 200        printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
 201                get_board_version (), pci_slot);
 202
 203        printf ("CPU Board Revision %d.%d (0x%04x)\n",
 204                MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
 205                MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
 206
 207        printf("PCI1: %d bit, %s MHz, %s\n",
 208                (pci1_32) ? 32 : 64,
 209                strmhz(buf, pci1_speed),
 210                pci1_clk_sel ? "sync" : "async");
 211
 212        if (pci_dual) {
 213                printf("PCI2: 32 bit, 66 MHz, %s\n",
 214                        pci2_clk_sel ? "sync" : "async");
 215        } else {
 216                printf("PCI2: disabled\n");
 217        }
 218
 219        /*
 220         * Initialize local bus.
 221         */
 222        local_bus_init ();
 223
 224        return 0;
 225}
 226
 227/*
 228 * Initialize Local Bus
 229 */
 230void
 231local_bus_init(void)
 232{
 233        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 234        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 235
 236        uint clkdiv;
 237        uint lbc_hz;
 238        sys_info_t sysinfo;
 239        uint temp_lbcdll;
 240
 241        /*
 242         * Errata LBC11.
 243         * Fix Local Bus clock glitch when DLL is enabled.
 244         *
 245         * If localbus freq is < 66MHz, DLL bypass mode must be used.
 246         * If localbus freq is > 133MHz, DLL can be safely enabled.
 247         * Between 66 and 133, the DLL is enabled with an override workaround.
 248         */
 249
 250        get_sys_info(&sysinfo);
 251        clkdiv = lbc->lcrr & LCRR_CLKDIV;
 252        lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
 253
 254        if (lbc_hz < 66) {
 255                lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
 256
 257        } else if (lbc_hz >= 133) {
 258                lbc->lcrr &= (~LCRR_DBYP);              /* DLL Enabled */
 259
 260        } else {
 261                lbc->lcrr &= (~LCRR_DBYP);      /* DLL Enabled */
 262                udelay(200);
 263
 264                /*
 265                 * Sample LBC DLL ctrl reg, upshift it to set the
 266                 * override bits.
 267                 */
 268                temp_lbcdll = gur->lbcdllcr;
 269                gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 270                asm("sync;isync;msync");
 271        }
 272}
 273
 274/*
 275 * Initialize SDRAM memory on the Local Bus.
 276 */
 277void lbc_sdram_init(void)
 278{
 279#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 280
 281        uint idx;
 282        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 283        uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 284        uint cpu_board_rev;
 285        uint lsdmr_common;
 286
 287        puts("LBC SDRAM: ");
 288        print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
 289                   "\n       ");
 290
 291        /*
 292         * Setup SDRAM Base and Option Registers
 293         */
 294        set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
 295        set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 296        lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 297        asm("msync");
 298
 299        lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 300        lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 301        asm("msync");
 302
 303        /*
 304         * Determine which address lines to use baed on CPU board rev.
 305         */
 306        cpu_board_rev = get_cpu_board_revision();
 307        lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 308        if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
 309                lsdmr_common |= LSDMR_BSMA1617;
 310        } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
 311                lsdmr_common |= LSDMR_BSMA1516;
 312        } else {
 313                /*
 314                 * Assume something unable to identify itself is
 315                 * really old, and likely has lines 16/17 mapped.
 316                 */
 317                lsdmr_common |= LSDMR_BSMA1617;
 318        }
 319
 320        /*
 321         * Issue PRECHARGE ALL command.
 322         */
 323        lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 324        asm("sync;msync");
 325        *sdram_addr = 0xff;
 326        ppcDcbf((unsigned long) sdram_addr);
 327        udelay(100);
 328
 329        /*
 330         * Issue 8 AUTO REFRESH commands.
 331         */
 332        for (idx = 0; idx < 8; idx++) {
 333                lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 334                asm("sync;msync");
 335                *sdram_addr = 0xff;
 336                ppcDcbf((unsigned long) sdram_addr);
 337                udelay(100);
 338        }
 339
 340        /*
 341         * Issue 8 MODE-set command.
 342         */
 343        lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 344        asm("sync;msync");
 345        *sdram_addr = 0xff;
 346        ppcDcbf((unsigned long) sdram_addr);
 347        udelay(100);
 348
 349        /*
 350         * Issue NORMAL OP command.
 351         */
 352        lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 353        asm("sync;msync");
 354        *sdram_addr = 0xff;
 355        ppcDcbf((unsigned long) sdram_addr);
 356        udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 357
 358#endif  /* enable SDRAM init */
 359}
 360
 361#ifdef CONFIG_PCI
 362/* For some reason the Tundra PCI bridge shows up on itself as a
 363 * different device.  Work around that by refusing to configure it
 364 */
 365void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
 366
 367static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 368        {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
 369        {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
 370        {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
 371                mpc85xx_config_via_usbide, {0,0,0}},
 372        {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
 373                mpc85xx_config_via_usb, {0,0,0}},
 374        {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
 375                mpc85xx_config_via_usb2, {0,0,0}},
 376        {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
 377                mpc85xx_config_via_power, {0,0,0}},
 378        {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
 379                mpc85xx_config_via_ac97, {0,0,0}},
 380        {},
 381};
 382
 383
 384static struct pci_controller hose[] = {
 385        {
 386        config_table: pci_mpc85xxcds_config_table,
 387        },
 388#ifdef CONFIG_MPC85XX_PCI2
 389        {},
 390#endif
 391};
 392
 393#endif
 394
 395void
 396pci_init_board(void)
 397{
 398#ifdef CONFIG_PCI
 399        pci_mpc85xx_init(hose);
 400#endif
 401}
 402
 403#if defined(CONFIG_OF_BOARD_SETUP)
 404void
 405ft_pci_setup(void *blob, bd_t *bd)
 406{
 407        int node, tmp[2];
 408        const char *path;
 409
 410        node = fdt_path_offset(blob, "/aliases");
 411        tmp[0] = 0;
 412        if (node >= 0) {
 413#ifdef CONFIG_PCI1
 414                path = fdt_getprop(blob, node, "pci0", NULL);
 415                if (path) {
 416                        tmp[1] = hose[0].last_busno - hose[0].first_busno;
 417                        do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 418                }
 419#endif
 420#ifdef CONFIG_MPC85XX_PCI2
 421                path = fdt_getprop(blob, node, "pci1", NULL);
 422                if (path) {
 423                        tmp[1] = hose[1].last_busno - hose[1].first_busno;
 424                        do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 425                }
 426#endif
 427        }
 428}
 429#endif
 430