LXR uboot/board/freescale/p1022ds/p1022ds.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2010-2012 Freescale Semiconductor, Inc.
   4 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   5 *          Timur Tabi <timur@freescale.com>
   6 */
   7
   8#include <common.h>
   9#include <command.h>
  10#include <env.h>
  11#include <init.h>
  12#include <pci.h>
  13#include <asm/processor.h>
  14#include <asm/mmu.h>
  15#include <asm/cache.h>
  16#include <asm/immap_85xx.h>
  17#include <asm/fsl_pci.h>
  18#include <fsl_ddr_sdram.h>
  19#include <asm/fsl_serdes.h>
  20#include <asm/io.h>
  21#include <linux/libfdt.h>
  22#include <fdt_support.h>
  23#include <fsl_mdio.h>
  24#include <tsec.h>
  25#include <asm/fsl_law.h>
  26#include <netdev.h>
  27#include <i2c.h>
  28#include <hwconfig.h>
  29
  30#include "../common/ngpixis.h"
  31
  32int board_early_init_f(void)
  33{
  34        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  35
  36        /* Set pmuxcr to allow both i2c1 and i2c2 */
  37        setbits_be32(&gur->pmuxcr, 0x1000);
  38#ifdef CONFIG_SYS_RAMBOOT
  39        setbits_be32(&gur->pmuxcr,
  40                in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
  41#endif
  42
  43        /* Read back the register to synchronize the write. */
  44        in_be32(&gur->pmuxcr);
  45
  46        /* Set the pin muxing to enable ETSEC2. */
  47        clrbits_be32(&gur->pmuxcr2, 0x001F8000);
  48
  49        /* Enable the SPI */
  50        clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
  51
  52        return 0;
  53}
  54
  55int checkboard(void)
  56{
  57        u8 sw;
  58
  59        printf("Board: P1022DS Sys ID: 0x%02x, "
  60               "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  61                in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  62
  63        sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  64
  65        switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
  66        case 0:
  67                printf ("vBank: %u\n", ((sw & 0x30) >> 4));
  68                break;
  69        case 1:
  70                printf ("NAND\n");
  71                break;
  72        case 2:
  73        case 3:
  74                puts ("Promjet\n");
  75                break;
  76        }
  77
  78        return 0;
  79}
  80
  81#define CONFIG_TFP410_I2C_ADDR  0x38
  82
  83/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
  84#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK       0x0c
  85#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK        0x03
  86
  87/* Route the I2C1 pins to the SSI port instead. */
  88#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI        0x08
  89
  90/* Choose the 12.288Mhz codec reference clock */
  91#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12          0x02
  92
  93/* Choose the 11.2896Mhz codec reference clock */
  94#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11          0x01
  95
  96/* Connect to USB2 */
  97#define CONFIG_PIXIS_BRDCFG0_USB2               0x10
  98/* Connect to TFM bus */
  99#define CONFIG_PIXIS_BRDCFG1_TDM                0x0c
 100/* Connect to SPI */
 101#define CONFIG_PIXIS_BRDCFG0_SPI                0x80
 102
 103int misc_init_r(void)
 104{
 105        u8 temp;
 106        const char *audclk;
 107        size_t arglen;
 108        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 109
 110        /* For DVI, enable the TFP410 Encoder. */
 111
 112        temp = 0xBF;
 113        if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
 114                return -1;
 115        if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
 116                return -1;
 117        debug("DVI Encoder Read: 0x%02x\n", temp);
 118
 119        temp = 0x10;
 120        if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
 121                return -1;
 122        if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
 123                return -1;
 124        debug("DVI Encoder Read: 0x%02x\n",temp);
 125
 126        /* Enable the USB2 in PMUXCR2 and FGPA */
 127        if (hwconfig("usb2")) {
 128                clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
 129                        MPC85xx_PMUXCR2_USB);
 130                setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
 131        }
 132
 133        /* tdm and audio can not enable simultaneous*/
 134        if (hwconfig("tdm") && hwconfig("audclk")){
 135                printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
 136                return -1;
 137        }
 138
 139        /* Enable the TDM in PMUXCR and FGPA */
 140        if (hwconfig("tdm")) {
 141                clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
 142                        MPC85xx_PMUXCR_TDM);
 143                setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
 144                /* TDM need some configration option by SPI */
 145                clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
 146                        MPC85xx_PMUXCR_SPI);
 147                setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
 148        }
 149
 150        /*
 151         * Enable the reference clock for the WM8776 codec, and route the MUX
 152         * pins for SSI. The default is the 12.288 MHz clock
 153         */
 154
 155        if (hwconfig("audclk")) {
 156                temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
 157                        CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
 158                temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
 159
 160                audclk = hwconfig_arg("audclk", &arglen);
 161                /* Check the first two chars only */
 162                if (audclk && (strncmp(audclk, "11", 2) == 0))
 163                        temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
 164                else
 165                        temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
 166                setbits_8(&pixis->brdcfg1, temp);
 167        }
 168
 169        return 0;
 170}
 171
 172/*
 173 * A list of PCI and SATA slots
 174 */
 175enum slot_id {
 176        SLOT_PCIE1 = 1,
 177        SLOT_PCIE2,
 178        SLOT_PCIE3,
 179        SLOT_PCIE4,
 180        SLOT_PCIE5,
 181        SLOT_SATA1,
 182        SLOT_SATA2
 183};
 184
 185/*
 186 * This array maps the slot identifiers to their names on the P1022DS board.
 187 */
 188static const char *slot_names[] = {
 189        [SLOT_PCIE1] = "Slot 1",
 190        [SLOT_PCIE2] = "Slot 2",
 191        [SLOT_PCIE3] = "Slot 3",
 192        [SLOT_PCIE4] = "Slot 4",
 193        [SLOT_PCIE5] = "Mini-PCIe",
 194        [SLOT_SATA1] = "SATA 1",
 195        [SLOT_SATA2] = "SATA 2",
 196};
 197
 198/*
 199 * This array maps a given SERDES configuration and SERDES device to the PCI or
 200 * SATA slot that it connects to.  This mapping is hard-coded in the FPGA.
 201 */
 202static u8 serdes_dev_slot[][SATA2 + 1] = {
 203        [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
 204        [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
 205        [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
 206                   [PCIE2] = SLOT_PCIE5 },
 207        [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
 208                   [PCIE2] = SLOT_PCIE3,
 209                   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
 210        [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
 211                   [PCIE2] = SLOT_PCIE3 },
 212        [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
 213                   [PCIE2] = SLOT_PCIE3,
 214                   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
 215        [0x1c] = { [PCIE1] = SLOT_PCIE1,
 216                   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
 217        [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
 218        [0x1f] = { [PCIE1] = SLOT_PCIE1 },
 219};
 220
 221
 222/*
 223 * Returns the name of the slot to which the PCIe or SATA controller is
 224 * connected
 225 */
 226const char *board_serdes_name(enum srds_prtcl device)
 227{
 228        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 229        u32 pordevsr = in_be32(&gur->pordevsr);
 230        unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
 231                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;
 232        enum slot_id slot = serdes_dev_slot[srds_cfg][device];
 233        const char *name = slot_names[slot];
 234
 235        if (name)
 236                return name;
 237        else
 238                return "Nothing";
 239}
 240
 241#ifdef CONFIG_PCI
 242void pci_init_board(void)
 243{
 244        fsl_pcie_init_board(0);
 245}
 246#endif
 247
 248int board_early_init_r(void)
 249{
 250        const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 251        int flash_esel = find_tlb_idx((void *)flashbase, 1);
 252
 253        /*
 254         * Remap Boot flash + PROMJET region to caching-inhibited
 255         * so that flash can be erased properly.
 256         */
 257
 258        /* Flush d-cache and invalidate i-cache of any FLASH data */
 259        flush_dcache();
 260        invalidate_icache();
 261
 262        if (flash_esel == -1) {
 263                /* very unlikely unless something is messed up */
 264                puts("Error: Could not find TLB for FLASH BASE\n");
 265                flash_esel = 2; /* give our best effort to continue */
 266        } else {
 267                /* invalidate existing TLB entry for flash + promjet */
 268                disable_tlb(flash_esel);
 269        }
 270
 271        set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 272                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 273                        0, flash_esel, BOOKE_PAGESZ_256M, 1);
 274
 275        return 0;
 276}
 277
 278/*
 279 * Initialize on-board and/or PCI Ethernet devices
 280 *
 281 * Returns:
 282 *      <0, error
 283 *       0, no ethernet devices found
 284 *      >0, number of ethernet devices initialized
 285 */
 286int board_eth_init(bd_t *bis)
 287{
 288        struct fsl_pq_mdio_info mdio_info;
 289        struct tsec_info_struct tsec_info[2];
 290        unsigned int num = 0;
 291
 292#ifdef CONFIG_TSEC1
 293        SET_STD_TSEC_INFO(tsec_info[num], 1);
 294        num++;
 295#endif
 296#ifdef CONFIG_TSEC2
 297        SET_STD_TSEC_INFO(tsec_info[num], 2);
 298        num++;
 299#endif
 300
 301        mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 302        mdio_info.name = DEFAULT_MII_NAME;
 303        fsl_pq_mdio_init(bis, &mdio_info);
 304
 305        return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
 306}
 307
 308#ifdef CONFIG_OF_BOARD_SETUP
 309/**
 310 * ft_codec_setup - fix up the clock-frequency property of the codec node
 311 *
 312 * Update the clock-frequency property based on the value of the 'audclk'
 313 * hwconfig option.  If audclk is not specified, then don't write anything
 314 * to the device tree, because it means that the codec clock is disabled.
 315 */
 316static void ft_codec_setup(void *blob, const char *compatible)
 317{
 318        const char *audclk;
 319        size_t arglen;
 320        u32 freq;
 321
 322        audclk = hwconfig_arg("audclk", &arglen);
 323        if (audclk) {
 324                if (strncmp(audclk, "11", 2) == 0)
 325                        freq = 11289600;
 326                else
 327                        freq = 12288000;
 328
 329                do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
 330                                       freq, 1);
 331        }
 332}
 333
 334int ft_board_setup(void *blob, bd_t *bd)
 335{
 336        phys_addr_t base;
 337        phys_size_t size;
 338
 339        ft_cpu_setup(blob, bd);
 340
 341        base = env_get_bootm_low();
 342        size = env_get_bootm_size();
 343
 344        fdt_fixup_memory(blob, (u64)base, (u64)size);
 345
 346#ifdef CONFIG_HAS_FSL_DR_USB
 347        fsl_fdt_fixup_dr_usb(blob, bd);
 348#endif
 349
 350        FT_FSL_PCI_SETUP;
 351
 352#ifdef CONFIG_FSL_SGMII_RISER
 353        fsl_sgmii_riser_fdt_fixup(blob);
 354#endif
 355
 356        /* Update the WM8776 node's clock frequency property */
 357        ft_codec_setup(blob, "wlf,wm8776");
 358
 359        return 0;
 360}
 361#endif
 362