LXR uboot/board/phytec/pcm052/pcm052.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2018
   4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
   5 *
   6 * Copyright 2013 Freescale Semiconductor, Inc.
   7 */
   8
   9#include <common.h>
  10#include <init.h>
  11#include <asm/io.h>
  12#include <asm/arch/imx-regs.h>
  13#include <asm/arch/iomux-vf610.h>
  14#include <asm/arch/ddrmc-vf610.h>
  15#include <asm/arch/crm_regs.h>
  16#include <asm/arch/clock.h>
  17#include <env.h>
  18#include <led.h>
  19#include <miiphy.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23static struct ddrmc_cr_setting pcm052_cr_settings[] = {
  24        /* not in the datasheets, but in the original code */
  25        { 0x00002000, 105 },
  26        { 0x00000020, 110 },
  27        /* AXI */
  28        { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
  29        { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
  30        { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
  31                   DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
  32        { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
  33                   DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
  34        { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
  35                   DDRMC_CR122_AXI0_PRIRLX(100), 122 },
  36        { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
  37                   DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
  38        { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
  39        { DDRMC_CR126_PHY_RDLAT(11), 126 },
  40        { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
  41        { DDRMC_CR137_PHYCTL_DL(2), 137 },
  42        { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
  43                   DDRMC_CR139_PHY_WRLV_DLL(3) |
  44                   DDRMC_CR139_PHY_WRLV_EN(3), 139 },
  45        { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
  46                   DDRMC_CR154_PAD_ZQ_MODE(1) |
  47                   DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
  48                   DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
  49        { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
  50        { DDRMC_CR158_TWR(6), 158 },
  51        { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
  52                   DDRMC_CR161_TODTH_WR(6), 161 },
  53        /* end marker */
  54        { 0, -1 }
  55};
  56
  57/* PHY settings -- most of them differ from default in imx-regs.h */
  58
  59#define PCM052_DDRMC_PHY_DQ_TIMING                      0x00002213
  60#define PCM052_DDRMC_PHY_CTRL                           0x00290000
  61#define PCM052_DDRMC_PHY_SLAVE_CTRL                     0x00002c00
  62#define PCM052_DDRMC_PHY_PROC_PAD_ODT                   0x00010020
  63
  64static struct ddrmc_phy_setting pcm052_phy_settings[] = {
  65        { PCM052_DDRMC_PHY_DQ_TIMING,  0 },
  66        { PCM052_DDRMC_PHY_DQ_TIMING, 16 },
  67        { PCM052_DDRMC_PHY_DQ_TIMING, 32 },
  68        { PCM052_DDRMC_PHY_DQ_TIMING, 48 },
  69        { DDRMC_PHY_DQS_TIMING,  1 },
  70        { DDRMC_PHY_DQS_TIMING, 17 },
  71        { DDRMC_PHY_DQS_TIMING, 33 },
  72        { DDRMC_PHY_DQS_TIMING, 49 },
  73        { PCM052_DDRMC_PHY_CTRL,  2 },
  74        { PCM052_DDRMC_PHY_CTRL, 18 },
  75        { PCM052_DDRMC_PHY_CTRL, 34 },
  76        { DDRMC_PHY_MASTER_CTRL,  3 },
  77        { DDRMC_PHY_MASTER_CTRL, 19 },
  78        { DDRMC_PHY_MASTER_CTRL, 35 },
  79        { PCM052_DDRMC_PHY_SLAVE_CTRL,  4 },
  80        { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
  81        { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
  82        { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
  83        { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
  84
  85        /* end marker */
  86        { 0, -1 }
  87};
  88
  89int dram_init(void)
  90{
  91#if defined(CONFIG_TARGET_PCM052)
  92
  93        static const struct ddr3_jedec_timings pcm052_ddr_timings = {
  94                .tinit             = 5,
  95                .trst_pwron        = 80000,
  96                .cke_inactive      = 200000,
  97                .wrlat             = 5,
  98                .caslat_lin        = 12,
  99                .trc               = 6,
 100                .trrd              = 4,
 101                .tccd              = 4,
 102                .tbst_int_interval = 4,
 103                .tfaw              = 18,
 104                .trp               = 6,
 105                .twtr              = 4,
 106                .tras_min          = 15,
 107                .tmrd              = 4,
 108                .trtp              = 4,
 109                .tras_max          = 14040,
 110                .tmod              = 12,
 111                .tckesr            = 4,
 112                .tcke              = 3,
 113                .trcd_int          = 6,
 114                .tras_lockout      = 1,
 115                .tdal              = 10,
 116                .bstlen            = 3,
 117                .tdll              = 512,
 118                .trp_ab            = 6,
 119                .tref              = 1542,
 120                .trfc              = 64,
 121                .tref_int          = 5,
 122                .tpdex             = 3,
 123                .txpdll            = 10,
 124                .txsnr             = 68,
 125                .txsr              = 506,
 126                .cksrx             = 5,
 127                .cksre             = 5,
 128                .freq_chg_en       = 1,
 129                .zqcl              = 256,
 130                .zqinit            = 512,
 131                .zqcs              = 64,
 132                .ref_per_zq        = 64,
 133                .zqcs_rotate       = 1,
 134                .aprebit           = 10,
 135                .cmd_age_cnt       = 255,
 136                .age_cnt           = 255,
 137                .q_fullness        = 0,
 138                .odt_rd_mapcs0     = 1,
 139                .odt_wr_mapcs0     = 1,
 140                .wlmrd             = 40,
 141                .wldqsen           = 25,
 142        };
 143
 144    const int row_diff = 2;
 145
 146#elif defined(CONFIG_TARGET_BK4R1)
 147
 148        static const struct ddr3_jedec_timings pcm052_ddr_timings = {
 149                .tinit             = 5,
 150                .trst_pwron        = 80000,
 151                .cke_inactive      = 200000,
 152                .wrlat             = 5,
 153                .caslat_lin        = 12,
 154                .trc               = 6,
 155                .trrd              = 4,
 156                .tccd              = 4,
 157                .tbst_int_interval = 0,
 158                .tfaw              = 16,
 159                .trp               = 6,
 160                .twtr              = 4,
 161                .tras_min          = 15,
 162                .tmrd              = 4,
 163                .trtp              = 4,
 164                .tras_max          = 28080,
 165                .tmod              = 12,
 166                .tckesr            = 4,
 167                .tcke              = 3,
 168                .trcd_int          = 6,
 169                .tras_lockout      = 1,
 170                .tdal              = 12,
 171                .bstlen            = 3,
 172                .tdll              = 512,
 173                .trp_ab            = 6,
 174                .tref              = 3120,
 175                .trfc              = 104,
 176                .tref_int          = 0,
 177                .tpdex             = 3,
 178                .txpdll            = 10,
 179                .txsnr             = 108,
 180                .txsr              = 512,
 181                .cksrx             = 5,
 182                .cksre             = 5,
 183                .freq_chg_en       = 1,
 184                .zqcl              = 256,
 185                .zqinit            = 512,
 186                .zqcs              = 64,
 187                .ref_per_zq        = 64,
 188                .zqcs_rotate       = 1,
 189                .aprebit           = 10,
 190                .cmd_age_cnt       = 255,
 191                .age_cnt           = 255,
 192                .q_fullness        = 0,
 193                .odt_rd_mapcs0     = 1,
 194                .odt_wr_mapcs0     = 1,
 195                .wlmrd             = 40,
 196                .wldqsen           = 25,
 197        };
 198
 199    const int row_diff = 1;
 200
 201#else /* Unknown PCM052 variant */
 202
 203#error DDR characteristics undefined for this target. Please define them.
 204
 205#endif
 206
 207        ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
 208                             pcm052_phy_settings, 1, row_diff);
 209
 210        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 211
 212        return 0;
 213}
 214
 215static void clock_init(void)
 216{
 217        struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
 218        struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
 219
 220        clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
 221                        CCM_CCGR0_UART1_CTRL_MASK);
 222        clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
 223                        CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
 224        clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
 225                        CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
 226                        CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
 227                        CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
 228                        CCM_CCGR2_QSPI0_CTRL_MASK);
 229        clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
 230                        CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
 231        clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
 232                        CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
 233                        CCM_CCGR4_GPC_CTRL_MASK);
 234        clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
 235                        CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
 236        clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
 237                        CCM_CCGR7_SDHC1_CTRL_MASK);
 238        clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
 239                        CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
 240        clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
 241                        CCM_CCGR10_NFC_CTRL_MASK);
 242
 243        clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
 244                        ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
 245        clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
 246                        ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
 247
 248        clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
 249                        CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
 250        clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
 251                        CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
 252                        CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
 253                        CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
 254                        CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
 255                        CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
 256                        CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
 257        clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
 258                        CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 259                        CCM_CACRR_ARM_CLK_DIV(0));
 260        clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
 261                        CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
 262                        CCM_CSCMR1_QSPI0_CLK_SEL(3) |
 263                        CCM_CSCMR1_NFC_CLK_SEL(0));
 264        clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
 265                        CCM_CSCDR1_RMII_CLK_EN);
 266        clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
 267                        CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
 268                        CCM_CSCDR2_NFC_EN);
 269        clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
 270                        CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
 271                        CCM_CSCDR3_QSPI0_X2_DIV(1) |
 272                        CCM_CSCDR3_QSPI0_X4_DIV(3) |
 273                        CCM_CSCDR3_NFC_PRE_DIV(5));
 274        clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 275                        CCM_CSCMR2_RMII_CLK_SEL(0));
 276}
 277
 278static void mscm_init(void)
 279{
 280        struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
 281        int i;
 282
 283        for (i = 0; i < MSCM_IRSPRC_NUM; i++)
 284                writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 285}
 286
 287int board_early_init_f(void)
 288{
 289        clock_init();
 290        mscm_init();
 291
 292        return 0;
 293}
 294
 295int board_init(void)
 296{
 297        struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
 298
 299        /* address of boot parameters */
 300        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 301
 302        /*
 303         * Enable external 32K Oscillator
 304         *
 305         * The internal clock experiences significant drift
 306         * so we must use the external oscillator in order
 307         * to maintain correct time in the hwclock
 308         */
 309        setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
 310
 311        return 0;
 312}
 313
 314#ifdef CONFIG_TARGET_BK4R1
 315void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 316{
 317        struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 318        struct fuse_bank *bank = &ocotp->bank[4];
 319        struct fuse_bank4_regs *fuse =
 320                (struct fuse_bank4_regs *)bank->fuse_regs;
 321        u32 value;
 322
 323        /*
 324         * BK4 has different layout of stored MAC address
 325         * than one used in imx_get_mac_from_fuse() @ generic.c
 326         */
 327
 328        switch (dev_id) {
 329        case 0:
 330                value = readl(&fuse->mac_addr1);
 331
 332                mac[0] = value >> 8;
 333                mac[1] = value;
 334
 335                value = readl(&fuse->mac_addr0);
 336                mac[2] = value >> 24;
 337                mac[3] = value >> 16;
 338                mac[4] = value >> 8;
 339                mac[5] = value;
 340                break;
 341        case 1:
 342                value = readl(&fuse->mac_addr2);
 343
 344                mac[0] = value >> 24;
 345                mac[1] = value >> 16;
 346                mac[2] = value >> 8;
 347                mac[3] = value;
 348
 349                value = readl(&fuse->mac_addr1);
 350                mac[4] = value >> 24;
 351                mac[5] = value >> 16;
 352                break;
 353        }
 354}
 355
 356int board_late_init(void)
 357{
 358        struct src *psrc = (struct src *)SRC_BASE_ADDR;
 359        u32 reg;
 360
 361        if (IS_ENABLED(CONFIG_LED))
 362                led_default_state();
 363
 364        /*
 365         * BK4r1 handle emergency/service SD card boot
 366         * Checking the SBMR1 register BOOTCFG1 byte:
 367         * NAND:
 368         *      bit [2] - NAND data width - 16
 369         *      bit [5] - NAND fast boot
 370         *      bit [7] = 1 - NAND as a source of booting
 371         * SD card (0x64):
 372         *      bit [4] = 0 - SD card source
 373         *      bit [6] = 1 - SD/MMC source
 374         */
 375
 376        reg = readl(&psrc->sbmr1);
 377        if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
 378            !(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
 379                printf("------ SD card boot -------\n");
 380                env_set_default("!LVFBootloader", 0);
 381                env_set("bootcmd",
 382                        "run prepare_install_bk4r1_envs; run install_bk4r1rs");
 383        }
 384
 385        return 0;
 386}
 387
 388/**
 389 * KSZ8081
 390 */
 391#define MII_KSZ8081_REFERENCE_CLOCK_SELECT      0x1f
 392#define RMII_50MHz_CLOCK        0x8180
 393
 394int board_phy_config(struct phy_device *phydev)
 395{
 396        /* Set 50 MHz reference clock */
 397        phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
 398                  RMII_50MHz_CLOCK);
 399
 400        return genphy_config(phydev);
 401}
 402#endif /* CONFIG_TARGET_BK4R1 */
 403
 404int checkboard(void)
 405{
 406#ifdef CONFIG_TARGET_BK4R1
 407        u32 *gpio3_pdir = (u32 *)(GPIO3_BASE_ADDR + 0x10);
 408
 409        /*
 410         * USB_RESET_N (PTC30 - GPIO103 - PORT3[7]):
 411         * L333 -> pull up added -> read 1
 412         * L320 -> no pull up -> read 0
 413         *
 414         * Default iomuxc_ptc30 value after reset: 0x300061 -> RCON28
 415         * - input enabled, pull (up/down) disabled
 416         */
 417        if (*gpio3_pdir & BIT(7))
 418                puts("Board: BK4r1 (L333)\n");
 419        else
 420                puts("Board: BK4r1 (L320)\n");
 421#else
 422        puts("Board: PCM-052\n");
 423#endif
 424        return 0;
 425}
 426