1
2
3
4
5
6
7
8
9#include <common.h>
10#include <init.h>
11
12#include <asm/arch/clock.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/ddrmc-vf610.h>
15#include <asm/arch/imx-regs.h>
16#include <asm/arch/iomux-vf610.h>
17#include <asm/gpio.h>
18#include <asm/io.h>
19#include <env.h>
20#include <fdt_support.h>
21#include <fsl_dcu_fb.h>
22#include <g_dnl.h>
23#include <jffs2/load_kernel.h>
24#include <mtd_node.h>
25#include <usb.h>
26
27#include "../common/tdx-common.h"
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#define PTC0_GPIO_45 45
32
33static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
34 { DDRMC_CR79_CTLUPD_AREF(1), 79 },
35
36 { DDRMC_CR105_RDLVL_DL_0(28), 105 },
37 { DDRMC_CR106_RDLVL_GTDL_0(24), 106 },
38 { DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 },
39 { DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 },
40
41
42 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
43 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
44 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
45 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
46 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
47 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
48 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
49 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
50 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
51 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
52 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
53 { DDRMC_CR126_PHY_RDLAT(8), 126 },
54 { DDRMC_CR132_WRLAT_ADJ(5) |
55 DDRMC_CR132_RDLAT_ADJ(6), 132 },
56 { DDRMC_CR137_PHYCTL_DL(2), 137 },
57 { DDRMC_CR138_PHY_WRLV_MXDL(256) |
58 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
59 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
60 DDRMC_CR139_PHY_WRLV_DLL(3) |
61 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
62 { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
63 { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
64 DDRMC_CR143_RDLV_MXDL(128), 143 },
65 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
66 DDRMC_CR144_PHY_RDLV_DLL(3) |
67 DDRMC_CR144_PHY_RDLV_EN(3), 144 },
68 { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
69 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
70 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
71 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
72 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
73 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
74
75 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
76 DDRMC_CR154_PAD_ZQ_MODE(1) |
77 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
78 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
79 { DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 },
80 { DDRMC_CR158_TWR(6), 158 },
81 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
82 DDRMC_CR161_TODTH_WR(2), 161 },
83
84 { 0, -1 }
85};
86
87int dram_init(void)
88{
89 static const struct ddr3_jedec_timings timings = {
90 .tinit = 5,
91 .trst_pwron = 80000,
92 .cke_inactive = 200000,
93 .wrlat = 5,
94 .caslat_lin = 12,
95 .trc = 21,
96 .trrd = 4,
97 .tccd = 4,
98 .tbst_int_interval = 0,
99 .tfaw = 20,
100 .trp = 6,
101 .twtr = 4,
102 .tras_min = 15,
103 .tmrd = 4,
104 .trtp = 4,
105 .tras_max = 28080,
106 .tmod = 12,
107 .tckesr = 4,
108 .tcke = 3,
109 .trcd_int = 6,
110 .tras_lockout = 0,
111 .tdal = 12,
112 .bstlen = 3,
113 .tdll = 512,
114
115
116 .trp_ab = 6,
117 .tref = 3120,
118 .trfc = 64,
119 .tref_int = 0,
120 .tpdex = 3,
121 .txpdll = 10,
122 .txsnr = 68,
123
124
125 .txsr = 506,
126
127
128 .cksrx = 5,
129 .cksre = 5,
130 .freq_chg_en = 0,
131 .zqcl = 256,
132 .zqinit = 512,
133 .zqcs = 64,
134 .ref_per_zq = 64,
135 .zqcs_rotate = 0,
136 .aprebit = 10,
137 .cmd_age_cnt = 64,
138 .age_cnt = 64,
139 .q_fullness = 7,
140 .odt_rd_mapcs0 = 0,
141 .odt_wr_mapcs0 = 1,
142 .wlmrd = 40,
143 .wldqsen = 25,
144 };
145
146 ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
147 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
148
149 return 0;
150}
151
152#ifdef CONFIG_VYBRID_GPIO
153static void setup_iomux_gpio(void)
154{
155 static const iomux_v3_cfg_t gpio_pads[] = {
156 VF610_PAD_PTA17__GPIO_7,
157 VF610_PAD_PTA20__GPIO_10,
158 VF610_PAD_PTA21__GPIO_11,
159 VF610_PAD_PTA30__GPIO_20,
160 VF610_PAD_PTA31__GPIO_21,
161 VF610_PAD_PTB0__GPIO_22,
162 VF610_PAD_PTB1__GPIO_23,
163 VF610_PAD_PTB6__GPIO_28,
164 VF610_PAD_PTB7__GPIO_29,
165 VF610_PAD_PTB8__GPIO_30,
166 VF610_PAD_PTB9__GPIO_31,
167 VF610_PAD_PTB12__GPIO_34,
168 VF610_PAD_PTB13__GPIO_35,
169 VF610_PAD_PTB16__GPIO_38,
170 VF610_PAD_PTB17__GPIO_39,
171 VF610_PAD_PTB18__GPIO_40,
172 VF610_PAD_PTB21__GPIO_43,
173 VF610_PAD_PTB22__GPIO_44,
174 VF610_PAD_PTC0__GPIO_45,
175 VF610_PAD_PTC1__GPIO_46,
176 VF610_PAD_PTC2__GPIO_47,
177 VF610_PAD_PTC3__GPIO_48,
178 VF610_PAD_PTC4__GPIO_49,
179 VF610_PAD_PTC5__GPIO_50,
180 VF610_PAD_PTC6__GPIO_51,
181 VF610_PAD_PTC7__GPIO_52,
182 VF610_PAD_PTC8__GPIO_53,
183 VF610_PAD_PTD31__GPIO_63,
184 VF610_PAD_PTD30__GPIO_64,
185 VF610_PAD_PTD29__GPIO_65,
186 VF610_PAD_PTD28__GPIO_66,
187 VF610_PAD_PTD27__GPIO_67,
188 VF610_PAD_PTD26__GPIO_68,
189 VF610_PAD_PTD25__GPIO_69,
190 VF610_PAD_PTD24__GPIO_70,
191 VF610_PAD_PTD9__GPIO_88,
192 VF610_PAD_PTD10__GPIO_89,
193 VF610_PAD_PTD11__GPIO_90,
194 VF610_PAD_PTD12__GPIO_91,
195 VF610_PAD_PTD13__GPIO_92,
196 VF610_PAD_PTB23__GPIO_93,
197 VF610_PAD_PTB26__GPIO_96,
198 VF610_PAD_PTB28__GPIO_98,
199 VF610_PAD_PTC30__GPIO_103,
200 VF610_PAD_PTA7__GPIO_134,
201 };
202
203 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
204}
205#endif
206
207#ifdef CONFIG_VIDEO_FSL_DCU_FB
208static void setup_iomux_fsl_dcu(void)
209{
210 static const iomux_v3_cfg_t dcu0_pads[] = {
211 VF610_PAD_PTE0__DCU0_HSYNC,
212 VF610_PAD_PTE1__DCU0_VSYNC,
213 VF610_PAD_PTE2__DCU0_PCLK,
214 VF610_PAD_PTE4__DCU0_DE,
215 VF610_PAD_PTE5__DCU0_R0,
216 VF610_PAD_PTE6__DCU0_R1,
217 VF610_PAD_PTE7__DCU0_R2,
218 VF610_PAD_PTE8__DCU0_R3,
219 VF610_PAD_PTE9__DCU0_R4,
220 VF610_PAD_PTE10__DCU0_R5,
221 VF610_PAD_PTE11__DCU0_R6,
222 VF610_PAD_PTE12__DCU0_R7,
223 VF610_PAD_PTE13__DCU0_G0,
224 VF610_PAD_PTE14__DCU0_G1,
225 VF610_PAD_PTE15__DCU0_G2,
226 VF610_PAD_PTE16__DCU0_G3,
227 VF610_PAD_PTE17__DCU0_G4,
228 VF610_PAD_PTE18__DCU0_G5,
229 VF610_PAD_PTE19__DCU0_G6,
230 VF610_PAD_PTE20__DCU0_G7,
231 VF610_PAD_PTE21__DCU0_B0,
232 VF610_PAD_PTE22__DCU0_B1,
233 VF610_PAD_PTE23__DCU0_B2,
234 VF610_PAD_PTE24__DCU0_B3,
235 VF610_PAD_PTE25__DCU0_B4,
236 VF610_PAD_PTE26__DCU0_B5,
237 VF610_PAD_PTE27__DCU0_B6,
238 VF610_PAD_PTE28__DCU0_B7,
239 };
240
241 imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
242}
243
244static void setup_tcon(void)
245{
246 setbits_le32(TCON0_BASE_ADDR, (1 << 29));
247}
248#endif
249
250static inline int is_colibri_vf61(void)
251{
252 struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
253
254
255
256
257
258 return !!mscm->cpxcfg1;
259}
260
261static void clock_init(void)
262{
263 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
264 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
265 u32 pfd_clk_sel, ddr_clk_sel;
266
267 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
268 CCM_CCGR0_UART0_CTRL_MASK);
269#ifdef CONFIG_FSL_DSPI
270 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
271#endif
272 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
273 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
274 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
275 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
276 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
277 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
278 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
279 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
280 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
281 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
282 CCM_CCGR4_GPC_CTRL_MASK);
283 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
284 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
285 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
286 CCM_CCGR7_SDHC1_CTRL_MASK);
287 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
288 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
289 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
290 CCM_CCGR10_NFC_CTRL_MASK);
291
292#ifdef CONFIG_USB_EHCI_VF
293 setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
294 setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
295
296 clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
297 ANADIG_PLL3_CTRL_POWERDOWN |
298 ANADIG_PLL3_CTRL_DIV_SELECT,
299 ANADIG_PLL3_CTRL_ENABLE);
300 clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
301 ANADIG_PLL7_CTRL_POWERDOWN |
302 ANADIG_PLL7_CTRL_DIV_SELECT,
303 ANADIG_PLL7_CTRL_ENABLE);
304#endif
305
306 clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
307 ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
308 ANADIG_PLL5_CTRL_DIV_SELECT);
309
310 if (is_colibri_vf61()) {
311 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
312 ANADIG_PLL2_CTRL_POWERDOWN,
313 ANADIG_PLL2_CTRL_ENABLE |
314 ANADIG_PLL2_CTRL_DIV_SELECT);
315 }
316
317 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
318 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
319
320 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
321 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
322
323
324 if (is_colibri_vf61()) {
325 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
326 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
327 } else {
328 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
329 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
330 }
331
332 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
333 CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
334 CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
335 CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
336 CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
337 ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
338 CCM_CCSR_SYS_CLK_SEL(4));
339
340 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
341 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
342 CCM_CACRR_ARM_CLK_DIV(0));
343 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
344 CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
345 CCM_CSCMR1_NFC_CLK_SEL(0));
346 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
347 CCM_CSCDR1_RMII_CLK_EN);
348 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
349 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
350 CCM_CSCDR2_NFC_EN);
351 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
352 CCM_CSCDR3_NFC_PRE_DIV(3));
353 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
354 CCM_CSCMR2_RMII_CLK_SEL(2));
355
356#ifdef CONFIG_VIDEO_FSL_DCU_FB
357 setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
358 setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
359#endif
360}
361
362static void mscm_init(void)
363{
364 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
365 int i;
366
367 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
368 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
369}
370
371int board_early_init_f(void)
372{
373 clock_init();
374 mscm_init();
375
376#ifdef CONFIG_VYBRID_GPIO
377 setup_iomux_gpio();
378#endif
379
380#ifdef CONFIG_VIDEO_FSL_DCU_FB
381 setup_tcon();
382 setup_iomux_fsl_dcu();
383#endif
384
385 return 0;
386}
387
388#ifdef CONFIG_BOARD_LATE_INIT
389int board_late_init(void)
390{
391 struct src *src = (struct src *)SRC_BASE_ADDR;
392
393 if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
394 == SRC_SBMR2_BMOD_SERIAL) {
395 printf("Serial Downloader recovery mode, disable autoboot\n");
396 env_set("bootdelay", "-1");
397 }
398
399 return 0;
400}
401#endif
402
403int board_init(void)
404{
405 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
406
407
408 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
409
410
411
412
413
414
415
416
417 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
418
419 return 0;
420}
421
422int checkboard(void)
423{
424 if (is_colibri_vf61())
425 puts("Model: Toradex Colibri VF61\n");
426 else
427 puts("Model: Toradex Colibri VF50\n");
428
429 return 0;
430}
431
432#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
433int ft_board_setup(void *blob, bd_t *bd)
434{
435#ifndef CONFIG_DM_VIDEO
436 int ret = 0;
437#endif
438#ifdef CONFIG_FDT_FIXUP_PARTITIONS
439 static const struct node_info nodes[] = {
440 { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, },
441 };
442
443
444 puts(" Updating MTD partitions...\n");
445 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
446#endif
447#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO)
448 ret = fsl_dcu_fixedfb_setup(blob);
449 if (ret)
450 return ret;
451#endif
452
453 return ft_common_board_setup(blob, bd);
454}
455#endif
456
457
458
459
460void board_preboot_os(void)
461{
462 gpio_request(PTC0_GPIO_45, "BL_ON");
463 gpio_direction_output(PTC0_GPIO_45, 0);
464}
465
